__projnav.log

this program performs the functonality of 4 bit alu

Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
m                                  | BUFGP                  | 16    |
u4:en1                             | NONE                   | 8     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 2.134ns (Maximum Frequency: 468.604MHz)
   Minimum input arrival time before clock: 6.844ns
   Maximum output required time after clock: 5.748ns
   Maximum combinational path delay: 6.189ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd g:\vijay_fpga_lab\4bit_alu/_ngo -i -p
xc3s50-pq208-4 alu_4bit.ngc alu_4bit.ngd 

Reading NGO file "G:/vijay_FPGA_LAB/4bit_alu/alu_4bit.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...
ERROR:NgdBuild:604 - logical block 'u1' with type 'testcnt' could not be
   resolved. A pin name misspelling can cause this, a missing edif or ngc file,
   or the misspelling of a type name. Symbol 'testcnt' is not supported in
   target 'spartan3'.
ERROR:NgdBuild:604 - logical block 'u2' with type 'testcnt' could not be
   resolved. A pin name misspelling can cause this, a missing edif or ngc file,
   or the misspelling of a type name. Symbol 'testcnt' is not supported in
   target 'spartan3'.
ERROR:NgdBuild:604 - logical block 'u4' with type 'dflip' could not be resolved.
   A pin name misspelling can cause this, a missing edif or ngc file, or the
   misspelling of a type name. Symbol 'dflip' is not supported in target
   'spartan3'.
ERROR:NgdBuild:604 - logical block 'u5' with type 'fbitaddr' could not be
   resolved. A pin name misspelling can cause this, a missing edif or ngc file,
   or the misspelling of a type name. Symbol 'fbitaddr' is not supported in
   target 'spartan3'.

NGDBUILD Design Results Summary:
  Number of errors:     4
  Number of warnings:   0

Total memory usage is 36100 kilobytes


One or more errors were found during NGDBUILD.  No NGD file will be written.

Writing NGDBUILD log file "alu_4bit.bld"...
ERROR: NGDBUILD failed
Process "Translate" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/fulladder.vhd in Library work.
Entity <fulladdr> (Architecture <Behavioral>) compiled.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/dflipflop.vhd in Library work.
Entity <dflipflop> (Architecture <Behavioral>) compiled.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/invtr.vhd in Library work.
Entity <invtr> (Architecture <Behavioral>) compiled.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/buff.vhd in Library work.
Entity <buff> (Architecture <Behavioral>) compiled.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/testcnt.vhd in Library work.
Entity <testcnt> (Architecture <Behavioral>) compiled.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd in Library work.
Entity <dflip> (Architecture <BEHAVIORAL>) compiled.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/fbitaddr.vhd in Library work.
Entity <fbitaddr> (Architecture <Behavioral>) compiled.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/4bit_alu.vhd in Library work.
Entity <alu_4bit> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <alu_4bit> (Architecture <behavioral>).
WARNING:Xst:819 - G:/vijay_FPGA_LAB/4bit_alu/4bit_alu.vhd line 91: The following signals are missing in the process sensitivity list:
   tempcout, tempdis.
WARNING:Xst:819 - G:/vijay_FPGA_LAB/4bit_alu/4bit_alu.vhd line 112: The following signals are missing in the process sensitivity list:
   ain, bin.
Entity <alu_4bit> analyzed. Unit <alu_4bit> generated.

Analyzing Entity <testcnt> (Architecture <behavioral>).
Entity <testcnt> analyzed. Unit <testcnt> generated.

Analyzing Entity <dflip> (Architecture <behavioral>).
ERROR:Xst:761 - G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd line 55: No default binding for component: <buff>. Ports <I,O> do not match.
--> 

Total memory usage is 55544 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/BUFF is now defined in a different file: was G:/vijay_FPGA_LAB/4bit_alu/buff.vhd, now is G:/vijay_FPGA_LAB/4bit_alu/../../GIRIJA/ALTERApgms/alu_4bit/buff.vhd
WARNING:HDLParsers:3215 - Unit work/BUFF/BEHAVIORAL is now defined in a different file: was G:/vijay_FPGA_LAB/4bit_alu/buff.vhd, now is G:/vijay_FPGA_LAB/4bit_alu/../../GIRIJA/ALTERApgms/alu_4bit/buff.vhd
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/fulladder.vhd in Library work.
Architecture behavioral of Entity fulladdr is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/dflipflop.vhd in Library work.
Architecture behavioral of Entity dflipflop is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/invtr.vhd in Library work.
Architecture behavioral of Entity invtr is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/../../GIRIJA/ALTERApgms/alu_4bit/buff.vhd in Library work.
Architecture behavioral of Entity buff is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/testcnt.vhd in Library work.
Architecture behavioral of Entity testcnt is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd in Library work.
Architecture behavioral of Entity dflip is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/fbitaddr.vhd in Library work.
Architecture behavioral of Entity fbitaddr is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/4bit_alu.vhd in Library work.
Entity <alu_4bit> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <alu_4bit> (Architecture <behavioral>).
WARNING:Xst:819 - G:/vijay_FPGA_LAB/4bit_alu/4bit_alu.vhd line 91: The following signals are missing in the process sensitivity list:
   tempcout, tempdis.
WARNING:Xst:819 - G:/vijay_FPGA_LAB/4bit_alu/4bit_alu.vhd line 112: The following signals are missing in the process sensitivity list:
   ain, bin.
Entity <alu_4bit> analyzed. Unit <alu_4bit> generated.

Analyzing Entity <testcnt> (Architecture <behavioral>).
Entity <testcnt> analyzed. Unit <testcnt> generated.

Analyzing Entity <dflip> (Architecture <behavioral>).
ERROR:Xst:761 - G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd line 55: No default binding for component: <buff>. Ports <I,O> do not match.
--> 

Total memory usage is 55544 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/fulladder.vhd in Library work.
Architecture behavioral of Entity fulladdr is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/dflipflop.vhd in Library work.
Architecture behavioral of Entity dflipflop is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/invtr.vhd in Library work.
Architecture behavioral of Entity invtr is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/../../GIRIJA/ALTERApgms/alu_4bit/buff.vhd in Library work.
Architecture behavioral of Entity buff is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/testcnt.vhd in Library work.
Architecture behavioral of Entity testcnt is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd in Library work.
ERROR:HDLParsers:800 - G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd Line 56. Type of I is incompatible with type of temp1.
ERROR:HDLParsers:800 - G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd Line 56. Type of O is incompatible with type of ben2.
--> 

Total memory usage is 46328 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/fulladder.vhd in Library work.
Architecture behavioral of Entity fulladdr is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/dflipflop.vhd in Library work.
Architecture behavioral of Entity dflipflop is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/invtr.vhd in Library work.
Architecture behavioral of Entity invtr is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/../../GIRIJA/ALTERApgms/alu_4bit/buff.vhd in Library work.
Architecture behavioral of Entity buff is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/testcnt.vhd in Library work.
Architecture behavioral of Entity testcnt is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd in Library work.
ERROR:HDLParsers:800 - G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd Line 46. Type of din is incompatible with type of temp1.
ERROR:HDLParsers:800 - G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd Line 50. Type of din is incompatible with type of temp1.
ERROR:HDLParsers:800 - G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd Line 50. Type of dout is incompatible with type of temp.
ERROR:HDLParsers:800 - G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd Line 53. Type of i is incompatible with type of temp.
ERROR:HDLParsers:800 - G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd Line 53. Type of o is incompatible with type of temp1.
ERROR:HDLParsers:800 - G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd Line 56. Type of O is incompatible with type of ben2.
--> 

Total memory usage is 46328 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/fulladder.vhd in Library work.
Architecture behavioral of Entity fulladdr is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/dflipflop.vhd in Library work.
Architecture behavioral of Entity dflipflop is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/invtr.vhd in Library work.
Architecture behavioral of Entity invtr is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/../../GIRIJA/ALTERApgms/alu_4bit/buff.vhd in Library work.
Architecture behavioral of Entity buff is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/testcnt.vhd in Library work.
Architecture behavioral of Entity testcnt is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd in Library work.
ERROR:HDLParsers:800 - G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd Line 50. Type of dout is incompatible with type of temp.
ERROR:HDLParsers:800 - G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd Line 53. Type of i is incompatible with type of temp.
ERROR:HDLParsers:800 - G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd Line 56. Type of I is incompatible with type of temp1.
ERROR:HDLParsers:800 - G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd Line 56. Type of O is incompatible with type of ben2.
--> 

Total memory usage is 46328 kilobytes


ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/fulladder.vhd in Library work.
Architecture behavioral of Entity fulladdr is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/dflipflop.vhd in Library work.
Architecture behavioral of Entity dflipflop is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/invtr.vhd in Library work.
Architecture behavioral of Entity invtr is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/../../GIRIJA/ALTERApgms/alu_4bit/buff.vhd in Library work.
Architecture behavioral of Entity buff is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/testcnt.vhd in Library work.
Architecture behavioral of Entity testcnt is up to date.
Compiling vhdl file G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd in Library work.
ERROR:HDLParsers:800 - G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd Line 56. Type of I is incompatible with type of temp1.
ERROR:HDLParsers:800 - G:/vijay_FPGA_LAB/4bit_alu/dflip.vhd Line 56. Type of O is incompatible with type of ben2.
-->