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Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file g:/vijay_fpga_lab/4bit_alu/4bit_alu.vhd in Library work.Entity <alu_4bit> (Architecture <Behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <alu_4bit> (Architecture <Behavioral>).WARNING:Xst:766 - g:/vijay_fpga_lab/4bit_alu/4bit_alu.vhd line 67: Generating a Black Box for component <testcnt>.WARNING:Xst:766 - g:/vijay_fpga_lab/4bit_alu/4bit_alu.vhd line 73: Generating a Black Box for component <testcnt>.WARNING:Xst:766 - g:/vijay_fpga_lab/4bit_alu/4bit_alu.vhd line 79: Generating a Black Box for component <dflip>.WARNING:Xst:766 - g:/vijay_fpga_lab/4bit_alu/4bit_alu.vhd line 83: Generating a Black Box for component <fbitaddr>.WARNING:Xst:819 - g:/vijay_fpga_lab/4bit_alu/4bit_alu.vhd line 91: The following signals are missing in the process sensitivity list: tempcout, tempdis.WARNING:Xst:819 - g:/vijay_fpga_lab/4bit_alu/4bit_alu.vhd line 112: The following signals are missing in the process sensitivity list: ain, bin.Entity <alu_4bit> analyzed. Unit <alu_4bit> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <alu_4bit>. Related source file is g:/vijay_fpga_lab/4bit_alu/4bit_alu.vhd.WARNING:Xst:646 - Signal <tempsout> is assigned but never used.WARNING:Xst:737 - Found 8-bit latch for signal <dis_out>.WARNING:Xst:737 - Found 4-bit latch for signal <dtemp>.WARNING:Xst:737 - Found 8-bit latch for signal <tempdis>.WARNING:Xst:737 - Found 4-bit latch for signal <stemp>. Found 16x8-bit ROM for signal <temp_out>. Found 4-bit adder for signal <$n0028> created at line 117. Found 17 1-bit 2-to-1 multiplexers. Summary: inferred 1 ROM(s). inferred 1 Adder/Subtracter(s). inferred 17 Multiplexer(s).Unit <alu_4bit> synthesized.INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# ROMs : 1 16x8-bit ROM : 1# Adders/Subtractors : 1 4-bit adder : 1# Latches : 4 4-bit latch : 2 8-bit latch : 2# Multiplexers : 4 8-bit 2-to-1 multiplexer : 1 4-bit 2-to-1 multiplexer : 2 1-bit 2-to-1 multiplexer : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <alu_4bit> ...Loading device for application Xst from file '3s50.nph' in environment E:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block alu_4bit, actual ratio is 3.WARNING:Xst:1426 - The value init of the FF/Latch tempdis_7 hinder the constant cleaning in the block alu_4bit. You should achieve better results by setting this init to 1.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 3s50pq208-5 Number of Slices: 26 out of 768 3% Number of Slice Flip Flops: 24 out of 1536 1% Number of 4 input LUTs: 45 out of 1536 2% Number of bonded IOBs: 29 out of 124 23% Number of GCLKs: 1 out of 8 12% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+m | BUFGP | 16 |u4:en1 | NONE | 8 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -5 Minimum period: 1.953ns (Maximum Frequency: 512.033MHz) Minimum input arrival time before clock: 6.232ns Maximum output required time after clock: 5.031ns Maximum combinational path delay: 5.554ns=========================================================================Completed process "Synthesize".
Started process "Translate".Command Line: ngdbuild -intstyle ise -dd g:\vijay_fpga_lab\4bit_alu/_ngo -i -pxc3s50-pq208-5 alu_4bit.ngc alu_4bit.ngd Reading NGO file "g:/vijay_fpga_lab/4bit_alu/alu_4bit.ngc" ...Reading component libraries for design expansion...Checking timing specifications ...Checking expanded design ...ERROR:NgdBuild:604 - logical block 'u1' with type 'testcnt' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'testcnt' is not supported in target 'spartan3'.ERROR:NgdBuild:604 - logical block 'u2' with type 'testcnt' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'testcnt' is not supported in target 'spartan3'.ERROR:NgdBuild:604 - logical block 'u4' with type 'dflip' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'dflip' is not supported in target 'spartan3'.ERROR:NgdBuild:604 - logical block 'u5' with type 'fbitaddr' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'fbitaddr' is not supported in target 'spartan3'.NGDBUILD Design Results Summary: Number of errors: 4 Number of warnings: 0Total memory usage is 36100 kilobytesOne or more errors were found during NGDBUILD. No NGD file will be written.Writing NGDBUILD log file "alu_4bit.bld"...ERROR: NGDBUILD failedProcess "Translate" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file g:/vijay_fpga_lab/4bit_alu/4bit_alu.vhd in Library work.Entity <alu_4bit> (Architecture <behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <alu_4bit> (Architecture <behavioral>).WARNING:Xst:766 - g:/vijay_fpga_lab/4bit_alu/4bit_alu.vhd line 67: Generating a Black Box for component <testcnt>.WARNING:Xst:766 - g:/vijay_fpga_lab/4bit_alu/4bit_alu.vhd line 73: Generating a Black Box for component <testcnt>.WARNING:Xst:766 - g:/vijay_fpga_lab/4bit_alu/4bit_alu.vhd line 79: Generating a Black Box for component <dflip>.WARNING:Xst:766 - g:/vijay_fpga_lab/4bit_alu/4bit_alu.vhd line 83: Generating a Black Box for component <fbitaddr>.WARNING:Xst:819 - g:/vijay_fpga_lab/4bit_alu/4bit_alu.vhd line 91: The following signals are missing in the process sensitivity list: tempcout, tempdis.WARNING:Xst:819 - g:/vijay_fpga_lab/4bit_alu/4bit_alu.vhd line 112: The following signals are missing in the process sensitivity list: ain, bin.Entity <alu_4bit> analyzed. Unit <alu_4bit> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <alu_4bit>. Related source file is g:/vijay_fpga_lab/4bit_alu/4bit_alu.vhd.WARNING:Xst:646 - Signal <tempsout> is assigned but never used.WARNING:Xst:737 - Found 8-bit latch for signal <dis_out>.WARNING:Xst:737 - Found 4-bit latch for signal <dtemp>.WARNING:Xst:737 - Found 8-bit latch for signal <tempdis>.WARNING:Xst:737 - Found 4-bit latch for signal <stemp>. Found 16x8-bit ROM for signal <temp_out>. Found 4-bit adder for signal <$n0028> created at line 117. Found 17 1-bit 2-to-1 multiplexers. Summary: inferred 1 ROM(s). inferred 1 Adder/Subtracter(s). inferred 17 Multiplexer(s).Unit <alu_4bit> synthesized.INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# ROMs : 1 16x8-bit ROM : 1# Adders/Subtractors : 1 4-bit adder : 1# Latches : 4 4-bit latch : 2 8-bit latch : 2# Multiplexers : 4 8-bit 2-to-1 multiplexer : 1 4-bit 2-to-1 multiplexer : 2 1-bit 2-to-1 multiplexer : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <alu_4bit> ...Loading device for application Xst from file '3s50.nph' in environment E:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block alu_4bit, actual ratio is 3.WARNING:Xst:1426 - The value init of the FF/Latch tempdis_7 hinder the constant cleaning in the block alu_4bit. You should achieve better results by setting this init to 1.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 3s50pq208-4 Number of Slices: 26 out of 768 3% Number of Slice Flip Flops: 24 out of 1536 1% Number of 4 input LUTs: 45 out of 1536 2% Number of bonded IOBs: 29 out of 124 23% Number of GCLKs: 1 out of 8 12% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+m | BUFGP | 16 |u4:en1 | NONE | 8 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -4 Minimum period: 2.134ns (Maximum Frequency: 468.604MHz) Minimum input arrival time before clock: 6.844ns Maximum output required time after clock: 5.748ns⌨️ 快捷键说明
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