dflip.vhd

来自「this program performs the functonality o」· VHDL 代码 · 共 63 行

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
--library UNISIM;
--use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity dflip is

   port ( clk : in    std_logic; 
          ben2  : out   std_logic; 
          en1   : out   std_logic);
end dflip;

architecture BEHAVIORAL of dflip is
	signal temp:std_logic;
	signal temp1: std_logic;
	signal temp2 :std_logic;
 	--attribute INIT       : STRING ;
   --attribute BOX_TYPE   : STRING ;
  
		component dflipflop is
	-- generic( init : bit; example:bit);	
   Port ( din : in std_logic;
           clk : in std_logic;
          dout : out std_logic
          );
end component;

  -- attribute init of fd : COMPONENT is "0";
  -- attribute BOX_TYPE of FD : COMPONENT is "BLACK_BOX";
   component invtr
      port ( i : in    std_logic; 
             o : out   std_logic);
   end component;
   
   component buff
      port ( I : in    std_logic;--_vector(3 downto 0); 
             O : out   std_logic);--_vector(3 downto 0));
   end component;
 
begin

   u1 : dflipflop

      port map (clk=>clk, din=>temp1, dout=>en1);
   
   XLXI_6 : dflipflop
--generic map(init =>'0')
      port map (clk=>clk, din=>temp1, dout=>temp);
   
   XLXI_7 : invtr
      port map (i=>temp, o=>temp1);
   
   XLXI_8 : buff
      --port map (I=>temp1, O=>ben2);
	 port map (i=>temp1,o=>ben2);
   
end BEHAVIORAL;