fulladder.vhd

this program performs the functonality of 4 bit alu

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fulladdr is
    Port ( cin : in std_logic;
           cout : out std_logic;
           a : in std_logic;
           b : in std_logic;
           s : out std_logic
			  );
end fulladdr;

architecture Behavioral of fulladdr is

begin

process(a,b,cin)

begin
	if cin = '1' then
	  if a = '1' then
			if b = '0' then
				s <= '0';
				cout <= '1';
			else
				s <= '1';
				cout <= '1';
			end if;
		else
			if b = '0' then
				s <= '1';
				cout <= '0';
			else
				s <= '0';
				cout <= '1';
			end if;
		end if;
	
		
	else
		if a = '1' then
			if b = '0' then
				s <= '1';
				cout <= '0';
			else
				s <= '0';
				cout <= '1';
			end if;
		else
			if b = '0' then
				s <= '0';
				cout <= '0';
			else
				s <= '1';
				cout <= '0';
			end if;
		end if;
	
	end if;
			
end process;

end Behavioral;