beep.tan.qmsg

实现beep发出1234567的音乐声音

{ "Info" "ITDB_FULL_TCO_RESULT" "clk beep buzzer:inst\|out 9.624 ns register " "Info: tco from clock \"clk\" to destination pin \"beep\" through register \"buzzer:inst\|out\" is 9.624 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.819 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 48 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 48; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "" { clk } "NODE_NAME" } "" } } { "beep.bdf" "" { Schematic "D:/beep/beep.bdf" { { 160 72 240 176 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns buzzer:inst\|out 2 REG LC_X10_Y9_N3 10 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X10_Y9_N3; Fanout = 10; REG Node = 'buzzer:inst\|out'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "2.656 ns" { clk buzzer:inst|out } "NODE_NAME" } "" } } { "buzzer.v" "" { Text "D:/beep/buzzer.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "3.819 ns" { clk buzzer:inst|out } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout buzzer:inst|out } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "buzzer.v" "" { Text "D:/beep/buzzer.v" 9 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.429 ns + Longest register pin " "Info: + Longest register to pin delay is 5.429 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns buzzer:inst\|out 1 REG LC_X10_Y9_N3 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y9_N3; Fanout = 10; REG Node = 'buzzer:inst\|out'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "" { buzzer:inst|out } "NODE_NAME" } "" } } { "buzzer.v" "" { Text "D:/beep/buzzer.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.107 ns) + CELL(2.322 ns) 5.429 ns beep 2 PIN PIN_144 0 " "Info: 2: + IC(3.107 ns) + CELL(2.322 ns) = 5.429 ns; Loc. = PIN_144; Fanout = 0; PIN Node = 'beep'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "5.429 ns" { buzzer:inst|out beep } "NODE_NAME" } "" } } { "beep.bdf" "" { Schematic "D:/beep/beep.bdf" { { 160 448 624 176 "beep" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 42.77 % ) " "Info: Total cell delay = 2.322 ns ( 42.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.107 ns ( 57.23 % ) " "Info: Total interconnect delay = 3.107 ns ( 57.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "5.429 ns" { buzzer:inst|out beep } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.429 ns" { buzzer:inst|out beep } { 0.000ns 3.107ns } { 0.000ns 2.322ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "3.819 ns" { clk buzzer:inst|out } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout buzzer:inst|out } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "5.429 ns" { buzzer:inst|out beep } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.429 ns" { buzzer:inst|out beep } { 0.000ns 3.107ns } { 0.000ns 2.322ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "buzzer:inst\|clk_div1\[0\] reset clk -1.458 ns register " "Info: th for register \"buzzer:inst\|clk_div1\[0\]\" (data pin = \"reset\", clock pin = \"clk\") is -1.458 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.819 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 48 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 48; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "" { clk } "NODE_NAME" } "" } } { "beep.bdf" "" { Schematic "D:/beep/beep.bdf" { { 160 72 240 176 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns buzzer:inst\|clk_div1\[0\] 2 REG LC_X13_Y8_N8 6 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X13_Y8_N8; Fanout = 6; REG Node = 'buzzer:inst\|clk_div1\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "2.656 ns" { clk buzzer:inst|clk_div1[0] } "NODE_NAME" } "" } } { "buzzer.v" "" { Text "D:/beep/buzzer.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "3.819 ns" { clk buzzer:inst|clk_div1[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout buzzer:inst|clk_div1[0] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "buzzer.v" "" { Text "D:/beep/buzzer.v" 38 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.498 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.498 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns reset 1 PIN PIN_93 36 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_93; Fanout = 36; PIN Node = 'reset'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "" { reset } "NODE_NAME" } "" } } { "beep.bdf" "" { Schematic "D:/beep/beep.bdf" { { 176 72 240 192 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.305 ns) + CELL(1.061 ns) 5.498 ns buzzer:inst\|clk_div1\[0\] 2 REG LC_X13_Y8_N8 6 " "Info: 2: + IC(3.305 ns) + CELL(1.061 ns) = 5.498 ns; Loc. = LC_X13_Y8_N8; Fanout = 6; REG Node = 'buzzer:inst\|clk_div1\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "4.366 ns" { reset buzzer:inst|clk_div1[0] } "NODE_NAME" } "" } } { "buzzer.v" "" { Text "D:/beep/buzzer.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.193 ns ( 39.89 % ) " "Info: Total cell delay = 2.193 ns ( 39.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.305 ns ( 60.11 % ) " "Info: Total interconnect delay = 3.305 ns ( 60.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "5.498 ns" { reset buzzer:inst|clk_div1[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.498 ns" { reset reset~combout buzzer:inst|clk_div1[0] } { 0.000ns 0.000ns 3.305ns } { 0.000ns 1.132ns 1.061ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "3.819 ns" { clk buzzer:inst|clk_div1[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout buzzer:inst|clk_div1[0] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "5.498 ns" { reset buzzer:inst|clk_div1[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.498 ns" { reset reset~combout buzzer:inst|clk_div1[0] } { 0.000ns 0.000ns 3.305ns } { 0.000ns 1.132ns 1.061ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 20 21:22:32 2006 " "Info: Processing ended: Mon Nov 20 21:22:32 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}