beep.tan.qmsg

实现beep发出1234567的音乐声音

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "beep.bdf" "" { Schematic "D:/beep/beep.bdf" { { 160 72 240 176 "clk" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register buzzer:inst\|clk_div2\[12\] register buzzer:inst\|clk_div2\[10\] 67.57 MHz 14.799 ns Internal " "Info: Clock \"clk\" has Internal fmax of 67.57 MHz between source register \"buzzer:inst\|clk_div2\[12\]\" and destination register \"buzzer:inst\|clk_div2\[10\]\" (period= 14.799 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.090 ns + Longest register register " "Info: + Longest register to register delay is 14.090 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns buzzer:inst\|clk_div2\[12\] 1 REG LC_X14_Y9_N6 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y9_N6; Fanout = 4; REG Node = 'buzzer:inst\|clk_div2\[12\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "" { buzzer:inst|clk_div2[12] } "NODE_NAME" } "" } } { "buzzer.v" "" { Text "D:/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.940 ns) + CELL(0.914 ns) 1.854 ns buzzer:inst\|Equal~1183 2 COMB LC_X14_Y9_N9 1 " "Info: 2: + IC(0.940 ns) + CELL(0.914 ns) = 1.854 ns; Loc. = LC_X14_Y9_N9; Fanout = 1; COMB Node = 'buzzer:inst\|Equal~1183'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "1.854 ns" { buzzer:inst|clk_div2[12] buzzer:inst|Equal~1183 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.803 ns) + CELL(0.200 ns) 3.857 ns buzzer:inst\|Equal~1184 3 COMB LC_X11_Y9_N1 3 " "Info: 3: + IC(1.803 ns) + CELL(0.200 ns) = 3.857 ns; Loc. = LC_X11_Y9_N1; Fanout = 3; COMB Node = 'buzzer:inst\|Equal~1184'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "2.003 ns" { buzzer:inst|Equal~1183 buzzer:inst|Equal~1184 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 4.362 ns buzzer:inst\|Equal~1188 4 COMB LC_X11_Y9_N2 3 " "Info: 4: + IC(0.305 ns) + CELL(0.200 ns) = 4.362 ns; Loc. = LC_X11_Y9_N2; Fanout = 3; COMB Node = 'buzzer:inst\|Equal~1188'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "0.505 ns" { buzzer:inst|Equal~1184 buzzer:inst|Equal~1188 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.175 ns) + CELL(0.200 ns) 5.737 ns buzzer:inst\|clk_div2\[9\]~2123 5 COMB LC_X12_Y9_N9 1 " "Info: 5: + IC(1.175 ns) + CELL(0.200 ns) = 5.737 ns; Loc. = LC_X12_Y9_N9; Fanout = 1; COMB Node = 'buzzer:inst\|clk_div2\[9\]~2123'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "1.375 ns" { buzzer:inst|Equal~1188 buzzer:inst|clk_div2[9]~2123 } "NODE_NAME" } "" } } { "buzzer.v" "" { Text "D:/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.709 ns) + CELL(0.740 ns) 7.186 ns buzzer:inst\|clk_div2\[9\]~2130 6 COMB LC_X12_Y9_N3 1 " "Info: 6: + IC(0.709 ns) + CELL(0.740 ns) = 7.186 ns; Loc. = LC_X12_Y9_N3; Fanout = 1; COMB Node = 'buzzer:inst\|clk_div2\[9\]~2130'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "1.449 ns" { buzzer:inst|clk_div2[9]~2123 buzzer:inst|clk_div2[9]~2130 } "NODE_NAME" } "" } } { "buzzer.v" "" { Text "D:/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 7.691 ns buzzer:inst\|clk_div2\[9\]~2124 7 COMB LC_X12_Y9_N4 1 " "Info: 7: + IC(0.305 ns) + CELL(0.200 ns) = 7.691 ns; Loc. = LC_X12_Y9_N4; Fanout = 1; COMB Node = 'buzzer:inst\|clk_div2\[9\]~2124'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "0.505 ns" { buzzer:inst|clk_div2[9]~2130 buzzer:inst|clk_div2[9]~2124 } "NODE_NAME" } "" } } { "buzzer.v" "" { Text "D:/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.534 ns) + CELL(0.200 ns) 8.425 ns buzzer:inst\|clk_div2\[9\]~2125 8 COMB LC_X12_Y9_N5 1 " "Info: 8: + IC(0.534 ns) + CELL(0.200 ns) = 8.425 ns; Loc. = LC_X12_Y9_N5; Fanout = 1; COMB Node = 'buzzer:inst\|clk_div2\[9\]~2125'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "0.734 ns" { buzzer:inst|clk_div2[9]~2124 buzzer:inst|clk_div2[9]~2125 } "NODE_NAME" } "" } } { "buzzer.v" "" { Text "D:/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.160 ns) + CELL(0.200 ns) 9.785 ns buzzer:inst\|clk_div2\[9\]~2126 9 COMB LC_X13_Y9_N2 1 " "Info: 9: + IC(1.160 ns) + CELL(0.200 ns) = 9.785 ns; Loc. = LC_X13_Y9_N2; Fanout = 1; COMB Node = 'buzzer:inst\|clk_div2\[9\]~2126'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "1.360 ns" { buzzer:inst|clk_div2[9]~2125 buzzer:inst|clk_div2[9]~2126 } "NODE_NAME" } "" } } { "buzzer.v" "" { Text "D:/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.735 ns) + CELL(0.740 ns) 11.260 ns buzzer:inst\|clk_div2\[9\]~2127 10 COMB LC_X13_Y9_N1 13 " "Info: 10: + IC(0.735 ns) + CELL(0.740 ns) = 11.260 ns; Loc. = LC_X13_Y9_N1; Fanout = 13; COMB Node = 'buzzer:inst\|clk_div2\[9\]~2127'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "1.475 ns" { buzzer:inst|clk_div2[9]~2126 buzzer:inst|clk_div2[9]~2127 } "NODE_NAME" } "" } } { "buzzer.v" "" { Text "D:/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.070 ns) + CELL(1.760 ns) 14.090 ns buzzer:inst\|clk_div2\[10\] 11 REG LC_X14_Y9_N4 8 " "Info: 11: + IC(1.070 ns) + CELL(1.760 ns) = 14.090 ns; Loc. = LC_X14_Y9_N4; Fanout = 8; REG Node = 'buzzer:inst\|clk_div2\[10\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "2.830 ns" { buzzer:inst|clk_div2[9]~2127 buzzer:inst|clk_div2[10] } "NODE_NAME" } "" } } { "buzzer.v" "" { Text "D:/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.354 ns ( 38.00 % ) " "Info: Total cell delay = 5.354 ns ( 38.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.736 ns ( 62.00 % ) " "Info: Total interconnect delay = 8.736 ns ( 62.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "14.090 ns" { buzzer:inst|clk_div2[12] buzzer:inst|Equal~1183 buzzer:inst|Equal~1184 buzzer:inst|Equal~1188 buzzer:inst|clk_div2[9]~2123 buzzer:inst|clk_div2[9]~2130 buzzer:inst|clk_div2[9]~2124 buzzer:inst|clk_div2[9]~2125 buzzer:inst|clk_div2[9]~2126 buzzer:inst|clk_div2[9]~2127 buzzer:inst|clk_div2[10] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "14.090 ns" { buzzer:inst|clk_div2[12] buzzer:inst|Equal~1183 buzzer:inst|Equal~1184 buzzer:inst|Equal~1188 buzzer:inst|clk_div2[9]~2123 buzzer:inst|clk_div2[9]~2130 buzzer:inst|clk_div2[9]~2124 buzzer:inst|clk_div2[9]~2125 buzzer:inst|clk_div2[9]~2126 buzzer:inst|clk_div2[9]~2127 buzzer:inst|clk_div2[10] } { 0.000ns 0.940ns 1.803ns 0.305ns 1.175ns 0.709ns 0.305ns 0.534ns 1.160ns 0.735ns 1.070ns } { 0.000ns 0.914ns 0.200ns 0.200ns 0.200ns 0.740ns 0.200ns 0.200ns 0.200ns 0.740ns 1.760ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.819 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 48 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 48; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "" { clk } "NODE_NAME" } "" } } { "beep.bdf" "" { Schematic "D:/beep/beep.bdf" { { 160 72 240 176 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns buzzer:inst\|clk_div2\[10\] 2 REG LC_X14_Y9_N4 8 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X14_Y9_N4; Fanout = 8; REG Node = 'buzzer:inst\|clk_div2\[10\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "2.656 ns" { clk buzzer:inst|clk_div2[10] } "NODE_NAME" } "" } } { "buzzer.v" "" { Text "D:/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "3.819 ns" { clk buzzer:inst|clk_div2[10] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout buzzer:inst|clk_div2[10] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.819 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 48 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 48; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "" { clk } "NODE_NAME" } "" } } { "beep.bdf" "" { Schematic "D:/beep/beep.bdf" { { 160 72 240 176 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns buzzer:inst\|clk_div2\[12\] 2 REG LC_X14_Y9_N6 4 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X14_Y9_N6; Fanout = 4; REG Node = 'buzzer:inst\|clk_div2\[12\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "2.656 ns" { clk buzzer:inst|clk_div2[12] } "NODE_NAME" } "" } } { "buzzer.v" "" { Text "D:/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "3.819 ns" { clk buzzer:inst|clk_div2[12] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout buzzer:inst|clk_div2[12] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "3.819 ns" { clk buzzer:inst|clk_div2[10] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout buzzer:inst|clk_div2[10] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "3.819 ns" { clk buzzer:inst|clk_div2[12] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout buzzer:inst|clk_div2[12] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "buzzer.v" "" { Text "D:/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "buzzer.v" "" { Text "D:/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "14.090 ns" { buzzer:inst|clk_div2[12] buzzer:inst|Equal~1183 buzzer:inst|Equal~1184 buzzer:inst|Equal~1188 buzzer:inst|clk_div2[9]~2123 buzzer:inst|clk_div2[9]~2130 buzzer:inst|clk_div2[9]~2124 buzzer:inst|clk_div2[9]~2125 buzzer:inst|clk_div2[9]~2126 buzzer:inst|clk_div2[9]~2127 buzzer:inst|clk_div2[10] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "14.090 ns" { buzzer:inst|clk_div2[12] buzzer:inst|Equal~1183 buzzer:inst|Equal~1184 buzzer:inst|Equal~1188 buzzer:inst|clk_div2[9]~2123 buzzer:inst|clk_div2[9]~2130 buzzer:inst|clk_div2[9]~2124 buzzer:inst|clk_div2[9]~2125 buzzer:inst|clk_div2[9]~2126 buzzer:inst|clk_div2[9]~2127 buzzer:inst|clk_div2[10] } { 0.000ns 0.940ns 1.803ns 0.305ns 1.175ns 0.709ns 0.305ns 0.534ns 1.160ns 0.735ns 1.070ns } { 0.000ns 0.914ns 0.200ns 0.200ns 0.200ns 0.740ns 0.200ns 0.200ns 0.200ns 0.740ns 1.760ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "3.819 ns" { clk buzzer:inst|clk_div2[10] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout buzzer:inst|clk_div2[10] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "3.819 ns" { clk buzzer:inst|clk_div2[12] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout buzzer:inst|clk_div2[12] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "buzzer:inst\|clk_div2\[11\] reset clk 6.267 ns register " "Info: tsu for register \"buzzer:inst\|clk_div2\[11\]\" (data pin = \"reset\", clock pin = \"clk\") is 6.267 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.753 ns + Longest pin register " "Info: + Longest pin to register delay is 9.753 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns reset 1 PIN PIN_93 36 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_93; Fanout = 36; PIN Node = 'reset'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "" { reset } "NODE_NAME" } "" } } { "beep.bdf" "" { Schematic "D:/beep/beep.bdf" { { 176 72 240 192 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.131 ns) + CELL(0.511 ns) 3.774 ns buzzer:inst\|clk_div2\[9\]~2120 2 COMB LC_X13_Y6_N2 1 " "Info: 2: + IC(2.131 ns) + CELL(0.511 ns) = 3.774 ns; Loc. = LC_X13_Y6_N2; Fanout = 1; COMB Node = 'buzzer:inst\|clk_div2\[9\]~2120'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "2.642 ns" { reset buzzer:inst|clk_div2[9]~2120 } "NODE_NAME" } "" } } { "buzzer.v" "" { Text "D:/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 4.279 ns buzzer:inst\|clk_div2\[9\]~2121 3 COMB LC_X13_Y6_N3 1 " "Info: 3: + IC(0.305 ns) + CELL(0.200 ns) = 4.279 ns; Loc. = LC_X13_Y6_N3; Fanout = 1; COMB Node = 'buzzer:inst\|clk_div2\[9\]~2121'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "0.505 ns" { buzzer:inst|clk_div2[9]~2120 buzzer:inst|clk_div2[9]~2121 } "NODE_NAME" } "" } } { "buzzer.v" "" { Text "D:/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.939 ns) + CELL(0.200 ns) 6.418 ns buzzer:inst\|clk_div2\[9\]~2122 4 COMB LC_X13_Y9_N0 1 " "Info: 4: + IC(1.939 ns) + CELL(0.200 ns) = 6.418 ns; Loc. = LC_X13_Y9_N0; Fanout = 1; COMB Node = 'buzzer:inst\|clk_div2\[9\]~2122'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "2.139 ns" { buzzer:inst|clk_div2[9]~2121 buzzer:inst|clk_div2[9]~2122 } "NODE_NAME" } "" } } { "buzzer.v" "" { Text "D:/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 6.923 ns buzzer:inst\|clk_div2\[9\]~2127 5 COMB LC_X13_Y9_N1 13 " "Info: 5: + IC(0.305 ns) + CELL(0.200 ns) = 6.923 ns; Loc. = LC_X13_Y9_N1; Fanout = 13; COMB Node = 'buzzer:inst\|clk_div2\[9\]~2127'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "0.505 ns" { buzzer:inst|clk_div2[9]~2122 buzzer:inst|clk_div2[9]~2127 } "NODE_NAME" } "" } } { "buzzer.v" "" { Text "D:/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.070 ns) + CELL(1.760 ns) 9.753 ns buzzer:inst\|clk_div2\[11\] 6 REG LC_X14_Y9_N5 8 " "Info: 6: + IC(1.070 ns) + CELL(1.760 ns) = 9.753 ns; Loc. = LC_X14_Y9_N5; Fanout = 8; REG Node = 'buzzer:inst\|clk_div2\[11\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "2.830 ns" { buzzer:inst|clk_div2[9]~2127 buzzer:inst|clk_div2[11] } "NODE_NAME" } "" } } { "buzzer.v" "" { Text "D:/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.003 ns ( 41.04 % ) " "Info: Total cell delay = 4.003 ns ( 41.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.750 ns ( 58.96 % ) " "Info: Total interconnect delay = 5.750 ns ( 58.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "9.753 ns" { reset buzzer:inst|clk_div2[9]~2120 buzzer:inst|clk_div2[9]~2121 buzzer:inst|clk_div2[9]~2122 buzzer:inst|clk_div2[9]~2127 buzzer:inst|clk_div2[11] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.753 ns" { reset reset~combout buzzer:inst|clk_div2[9]~2120 buzzer:inst|clk_div2[9]~2121 buzzer:inst|clk_div2[9]~2122 buzzer:inst|clk_div2[9]~2127 buzzer:inst|clk_div2[11] } { 0.000ns 0.000ns 2.131ns 0.305ns 1.939ns 0.305ns 1.070ns } { 0.000ns 1.132ns 0.511ns 0.200ns 0.200ns 0.200ns 1.760ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "buzzer.v" "" { Text "D:/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.819 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 48 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 48; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "" { clk } "NODE_NAME" } "" } } { "beep.bdf" "" { Schematic "D:/beep/beep.bdf" { { 160 72 240 176 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns buzzer:inst\|clk_div2\[11\] 2 REG LC_X14_Y9_N5 8 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X14_Y9_N5; Fanout = 8; REG Node = 'buzzer:inst\|clk_div2\[11\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "2.656 ns" { clk buzzer:inst|clk_div2[11] } "NODE_NAME" } "" } } { "buzzer.v" "" { Text "D:/beep/buzzer.v" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "3.819 ns" { clk buzzer:inst|clk_div2[11] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout buzzer:inst|clk_div2[11] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "9.753 ns" { reset buzzer:inst|clk_div2[9]~2120 buzzer:inst|clk_div2[9]~2121 buzzer:inst|clk_div2[9]~2122 buzzer:inst|clk_div2[9]~2127 buzzer:inst|clk_div2[11] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.753 ns" { reset reset~combout buzzer:inst|clk_div2[9]~2120 buzzer:inst|clk_div2[9]~2121 buzzer:inst|clk_div2[9]~2122 buzzer:inst|clk_div2[9]~2127 buzzer:inst|clk_div2[11] } { 0.000ns 0.000ns 2.131ns 0.305ns 1.939ns 0.305ns 1.070ns } { 0.000ns 1.132ns 0.511ns 0.200ns 0.200ns 0.200ns 1.760ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "beep" "UNKNOWN" "V1" "D:/beep/db/beep.quartus_db" { Floorplan "D:/beep/" "" "3.819 ns" { clk buzzer:inst|clk_div2[11] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout buzzer:inst|clk_div2[11] } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}