📄 calibip.v
字号:
/***********************************************************************************
-- Actel Corporation Proprietary and Confidential
-- Copyright 2007 Actel Corporation. All rights reserved.
--
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
-- IN ADVANCE IN WRITING.
--
-- Revision: 2.1
-- SVN Revision Information:
-- SVN $Revision: $
-- SVN $Date: $
--
-- Resolved SARs
-- SAR Date Who Description
--
*************************************************************************************/
`timescale 1ns/1ps
module
calibip
#
(
parameter
G_DEBUG
=
0
,
parameter
G_USE_SRAM_TILES
=
0
,
parameter
G_WIDTH_GAIN
=
11
,
parameter
G_WIDTH_OFFSET
=
8
,
parameter
G_ADC_BITS_8_10_12
=
0
,
parameter
G_OPTIMIZATION
=
0
,
parameter
G_SATURATE
=
1
)
(
input
wire
CLK,
input
wire
RESET_N,
input
wire
INIT_CLK,
input
wire
[
8
:
0
]
INIT_DATA,
input
wire
[
10
:
0
]
INIT_ADDR,
input
wire
INIT_ROM_WEN,
input
wire
INIT_COEFF_WEN,
input
wire
INIT_DONE,
output
wire
ADC_CH_ERROR,
output
wire
BUSY_CALIB,
output
wire
DATAVALID_CALIB,
output
wire
[
11
:
0
]
ADC_RESULT_CALIB,
input
wire
ADC_START,
input
wire
[
4
:
0
]
CH_NUMBER,
input
wire
BUSY,
input
wire
DATAVALID,
input
wire
[
11
:
0
]
ADC_RESULT
)
/* synthesis syn_maxfan=1000 */
;
wire
[
10
:
0
]
sv_M
;
wire
[
7
:
0
]
sv_C
;
wire
S_CLK_IN
;
assign
S_CLK_IN
=
CLK
;
wire
S_RESET_N_IN
;
assign
S_RESET_N_IN
=
RESET_N
;
wire
S_INIT_CLK_IN
;
assign
S_INIT_CLK_IN
=
INIT_CLK
;
wire
[
8
:
0
]
SV_INIT_DATA_IN
;
assign
SV_INIT_DATA_IN
=
INIT_DATA
;
wire
[
10
:
0
]
SV_INIT_ADDR_IN
;
assign
SV_INIT_ADDR_IN
=
INIT_ADDR
;
wire
S_INIT_ROM_WEN_IN
;
assign
S_INIT_ROM_WEN_IN
=
INIT_ROM_WEN
;
wire
S_INIT_COEFF_WEN_IN
;
assign
S_INIT_COEFF_WEN_IN
=
INIT_COEFF_WEN
;
wire
S_INIT_DONE_IN
;
assign
S_INIT_DONE_IN
=
INIT_DONE
;
wire
S_ADC_CH_ERROR_OUT
;
assign
ADC_CH_ERROR
=
S_ADC_CH_ERROR_OUT
;
wire
S_BUSY_CALIB_OUT
;
assign
BUSY_CALIB
=
S_BUSY_CALIB_OUT
;
wire
S_DATAVALID_CALIB_OUT
;
assign
DATAVALID_CALIB
=
S_DATAVALID_CALIB_OUT
;
wire
[
11
:
0
]
SV_ADC_RESULT_CALIB_OUT
;
assign
ADC_RESULT_CALIB
=
SV_ADC_RESULT_CALIB_OUT
;
wire
S_ADC_START_IN
;
assign
S_ADC_START_IN
=
ADC_START
;
wire
[
4
:
0
]
SV_CH_NUMBER_IN
;
assign
SV_CH_NUMBER_IN
=
CH_NUMBER
;
wire
S_BUSY_IN
;
assign
S_BUSY_IN
=
BUSY
;
wire
S_DATAVALID_IN
;
assign
S_DATAVALID_IN
=
DATAVALID
;
wire
[
11
:
0
]
SV_ADC_RESULT_IN
;
assign
SV_ADC_RESULT_IN
=
ADC_RESULT
;
calibip_CLRAM
#
(
.G_DEBUG
(
G_DEBUG
)
,
.G_USE_SRAM_TILES
(
G_USE_SRAM_TILES
)
)
u_clram
(
.S_CLK_IN
(
S_CLK_IN
)
,
.S_RESET_N_IN
(
S_RESET_N_IN
)
,
.S_INIT_CLK_IN
(
S_INIT_CLK_IN
)
,
.SV_INIT_DATA_IN
(
SV_INIT_DATA_IN
)
,
.SV_INIT_ADDR_IN
(
SV_INIT_ADDR_IN
)
,
.S_INIT_ROM_WEN_IN
(
S_INIT_ROM_WEN_IN
)
,
.S_INIT_COEFF_WEN_IN
(
S_INIT_COEFF_WEN_IN
)
,
.S_INIT_DONE_IN
(
S_INIT_DONE_IN
)
,
.S_ADC_CH_ERROR_OUT
(
S_ADC_CH_ERROR_OUT
)
,
.S_ADC_START_IN
(
S_ADC_START_IN
)
,
.SV_CH_NUMBER_IN
(
SV_CH_NUMBER_IN
)
,
.SV_M_OUT
(
sv_M
)
,
.SV_C_OUT
(
sv_C
)
)
;
COMPUTE_BLOCK
#
(
.G_WIDTH_GAIN
(
G_WIDTH_GAIN
)
,
.G_WIDTH_OFFSET
(
G_WIDTH_OFFSET
)
,
.G_ADC_BITS_8_10_12
(
G_ADC_BITS_8_10_12
)
,
.G_OPTIMIZATION
(
G_OPTIMIZATION
)
,
.G_SATURATE
(
G_SATURATE
)
)
u_compute
(
.SV_ADC_RESULT_IN
(
SV_ADC_RESULT_IN
)
,
.SV_GAIN_IN
(
sv_M
)
,
.SV_OFF_SET_IN
(
sv_C
)
,
.S_CLK_IN
(
S_CLK_IN
)
,
.S_RST_N_IN
(
S_RESET_N_IN
)
,
.S_BUSY_IN
(
S_BUSY_IN
)
,
.S_DATAVALID_IN
(
S_DATAVALID_IN
)
,
.S_BUSY_CALIB_OUT
(
S_BUSY_CALIB_OUT
)
,
.S_DATAVALID_CALIB_OUT
(
S_DATAVALID_CALIB_OUT
)
,
.SV_ADC_RESULT_CALIB_OUT
(
SV_ADC_RESULT_CALIB_OUT
)
)
;
endmodule
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -