calibip_clram.v

这是一个在Fusion系列的AFS600的FPGA

/***********************************************************************************             
-- Actel Corporation Proprietary and Confidential                                                
-- Copyright 2007 Actel Corporation. All rights reserved.
--                                                                                               
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN                              
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED                              
-- IN ADVANCE IN WRITING.                                                                        
--                                                                                               
-- Revision: 4.0 
-- SVN Revision Information:
-- SVN $Revision: $                                   
-- SVN $Date: $
-- 
-- Resolved SARs
-- SAR Date Who Description
--                                                                
*************************************************************************************/
`timescale 1ns/1ps
module
calibip_CLRAM
#
(
parameter
G_DEBUG
=
1
'b
0
,
parameter
G_USE_SRAM_TILES
=
1
'b
0
)
(
input
wire
S_CLK_IN,
input
wire
S_RESET_N_IN,
input
wire
S_INIT_CLK_IN,
input
wire
[
8
:
0
]
SV_INIT_DATA_IN,
input
wire
[
10
:
0
]
SV_INIT_ADDR_IN,
input
wire
S_INIT_ROM_WEN_IN,
input
wire
S_INIT_COEFF_WEN_IN,
input
wire
S_INIT_DONE_IN,
output
wire
S_ADC_CH_ERROR_OUT,
input
wire
S_ADC_START_IN,
input
wire
[
4
:
0
]
SV_CH_NUMBER_IN,
output
reg
[
10
:
0
]
SV_M_OUT,
output
reg
[
7
:
0
]
SV_C_OUT
)
;
reg
[
4
:
0
]
CCALIBIIl1
;
reg
[
4
:
0
]
CCALIBlIl1
;
reg
[
4
:
0
]
CCALIBOll1
;
reg
[
4
:
0
]
CCALIBIll1
;
reg
[
5
:
0
]
CCALIBlll1
;
reg
CCALIBO0l1
;
reg
CCALIBI0l1
;
wire
[
8
:
0
]
CCALIBl0l1
;
wire
[
8
:
0
]
CCALIBO1l1
;
wire
CCALIBI1l1
;
wire
CCALIBl1l1
;
wire
[
8
:
0
]
CCALIBOO01
;
wire
CCALIBIO01
;
wire
CCALIBlO01
;
wire
CCALIBOI01
;
wire
CCALIBII01
;
wire
[
8
:
0
]
CCALIBlI01
;
generate
if
(
G_USE_SRAM_TILES
==
0
)
begin
CCALIBOl01
CCALIBIl01
(
.CCALIBll01
(
S_CLK_IN
)
,
.CCALIBO001
(
S_CLK_IN
)
,
.CCALIBI001
(
CCALIBl0l1
)
,
.CCALIBl001
(
CCALIBO1l1
)
,
.CCALIBO101
(
CCALIBI1l1
)
,
.CCALIBI101
(
CCALIBl1l1
)
,
.CCALIBl101
(
SV_INIT_DATA_IN
)
,
.CCALIBOO11
(
CCALIBOO01
)
)
;
end
else
begin
end
endgenerate
assign
CCALIBI1l1
=
S_INIT_ROM_WEN_IN
||
CCALIBIO01
;
assign
CCALIBIO01
=
S_INIT_COEFF_WEN_IN
&&
CCALIBOI01
&&
CCALIBlO01
;
assign
CCALIBOI01
=
(
CCALIBIIl1
[
4
:
0
]
!=
5
'h
1F
)
;
assign
CCALIBlO01
=
SV_INIT_ADDR_IN
[
10
:
2
]
==
CCALIBOO01
[
8
:
0
]
;
assign
CCALIBII01
=
S_INIT_ROM_WEN_IN
&&
!
S_INIT_COEFF_WEN_IN
;
assign
CCALIBl0l1
[
8
:
0
]
=
(
CCALIBII01
)
?
SV_INIT_ADDR_IN
[
8
:
0
]
:
{
2
'b
10
,
CCALIBIIl1
[
4
:
0
]
,
SV_INIT_ADDR_IN
[
1
:
0
]
}
;
always
@
(
posedge
S_CLK_IN
or
negedge
S_RESET_N_IN
)
begin
if
(
S_RESET_N_IN
==
1
'b
0
)
CCALIBIIl1
<=
5
'h
00
;
else
CCALIBIIl1
<=
CCALIBlIl1
;
end
assign
CCALIBl1l1
=
1
'b
1
;
always
@
(
posedge
S_CLK_IN
or
negedge
S_RESET_N_IN
)
begin
if
(
S_RESET_N_IN
==
1
'b
0
)
CCALIBlll1
<=
6
'h
00
;
else
begin
CCALIBlll1
<=
{
CCALIBlll1
[
4
:
0
]
,
S_ADC_START_IN
}
;
end
end
assign
CCALIBO1l1
[
8
:
0
]
=
(
S_INIT_DONE_IN
)
?
CCALIBlI01
[
8
:
0
]
:
{
4
'h
0
,
CCALIBlIl1
[
4
:
0
]
}
;
assign
CCALIBlI01
[
8
:
0
]
=
(
CCALIBlll1
[
0
]
)
?
{
4
'h
4
,
CCALIBIll1
[
4
:
0
]
}
:
{
2
'b
10
,
CCALIBOll1
[
4
:
0
]
,
CCALIBlll1
[
4
:
3
]
}
;
always
@
(
posedge
S_CLK_IN
or
negedge
S_RESET_N_IN
)
begin
if
(
S_RESET_N_IN
==
1
'b
0
)
begin
CCALIBlIl1
<=
5
'h
00
;
CCALIBI0l1
<=
1
'b
0
;
end
else
begin
if
(
CCALIBI0l1
==
1
'b
1
)
begin
CCALIBlIl1
<=
CCALIBlIl1
+
1
;
end
CCALIBI0l1
<=
CCALIBIO01
&&
(
SV_INIT_ADDR_IN
[
1
:
0
]
==
2
'b
01
)
;
end
end
always
@
(
posedge
S_CLK_IN
or
negedge
S_RESET_N_IN
)
begin
if
(
S_RESET_N_IN
==
1
'b
0
)
CCALIBIll1
<=
5
'h
00
;
else
begin
if
(
S_ADC_START_IN
==
1
'b
1
)
CCALIBIll1
<=
SV_CH_NUMBER_IN
;
end
end
always
@
(
posedge
S_CLK_IN
or
negedge
S_RESET_N_IN
)
begin
if
(
S_RESET_N_IN
==
1
'b
0
)
CCALIBOll1
<=
5
'h
00
;
else
begin
if
(
CCALIBlll1
[
1
]
==
1
'b
1
)
CCALIBOll1
<=
CCALIBOO01
[
4
:
0
]
;
end
end
always
@
(
posedge
S_CLK_IN
or
negedge
S_RESET_N_IN
)
begin
if
(
S_RESET_N_IN
==
1
'b
0
)
begin
SV_M_OUT
<=
11
'h
400
;
SV_C_OUT
<=
8
'h
00
;
end
else
begin
if
(
CCALIBlll1
[
4
]
==
1
'b
1
)
SV_M_OUT
[
10
:
3
]
<=
CCALIBOO01
[
7
:
0
]
;
if
(
CCALIBlll1
[
3
]
==
1
'b
1
)
SV_M_OUT
[
2
:
0
]
<=
CCALIBOO01
[
7
:
5
]
;
if
(
CCALIBlll1
[
5
]
==
1
'b
1
)
SV_C_OUT
[
7
:
0
]
<=
CCALIBOO01
[
7
:
0
]
;
end
end
generate
if
(
G_DEBUG
==
1
)
always
@
(
posedge
S_CLK_IN
or
negedge
S_RESET_N_IN
)
begin
if
(
S_RESET_N_IN
==
1
'b
0
)
begin
CCALIBO0l1
<=
1
'b
0
;
end
else
begin
CCALIBO0l1
<=
&
CCALIBOll1
[
4
:
0
]
;
end
end
assign
S_ADC_CH_ERROR_OUT
=
CCALIBO0l1
;
endgenerate
endmodule