display.vhd

多功能计时器,具有校准

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY display IS
PORT(
in_data    : IN     STD_LOGIC_VECTOR(3 DOWNTO 0);
out_data   : OUT    STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END display;

ARCHITECTURE rtl of display IS
BEGIN
PROCESS(in_data)
BEGIN
CASE in_data IS
WHEN "0000"=>out_data<="0111111";
WHEN "0001"=>out_data<="0000110";
WHEN "0010"=>out_data<="1011011";
WHEN "0011"=>out_data<="1001111";
WHEN "0100"=>out_data<="1100110";
WHEN "0101"=>out_data<="1101101";
WHEN "0110"=>out_data<="1111100";
WHEN "0111"=>out_data<="0000111";
WHEN "1000"=>out_data<="1111111";
WHEN "1001"=>out_data<="1100111";
WHEN OTHERS=>out_data<="0000000";
END CASE;
END PROCESS;
END rtl;