📄 timer.tan.qmsg
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "MODE register counter24:HOUR_CONTROL\|LOW_REG\[2\] register counter24:HOUR_CONTROL\|HIGH_REG\[1\] 447.43 MHz 2.235 ns Internal " "Info: Clock \"MODE\" has Internal fmax of 447.43 MHz between source register \"counter24:HOUR_CONTROL\|LOW_REG\[2\]\" and destination register \"counter24:HOUR_CONTROL\|HIGH_REG\[1\]\" (period= 2.235 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.869 ns + Longest register register " "Info: + Longest register to register delay is 1.869 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter24:HOUR_CONTROL\|LOW_REG\[2\] 1 REG LCFF_X14_Y9_N15 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y9_N15; Fanout = 11; REG Node = 'counter24:HOUR_CONTROL\|LOW_REG\[2\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { counter24:HOUR_CONTROL|LOW_REG[2] } "NODE_NAME" } } { "counter24.vhd" "" { Text "F:/clock/counter24.vhd" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.276 ns) + CELL(0.346 ns) 0.622 ns counter24:HOUR_CONTROL\|Equal0~26 2 COMB LCCOMB_X14_Y9_N20 3 " "Info: 2: + IC(0.276 ns) + CELL(0.346 ns) = 0.622 ns; Loc. = LCCOMB_X14_Y9_N20; Fanout = 3; COMB Node = 'counter24:HOUR_CONTROL\|Equal0~26'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.622 ns" { counter24:HOUR_CONTROL|LOW_REG[2] counter24:HOUR_CONTROL|Equal0~26 } "NODE_NAME" } } { "d:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.215 ns) + CELL(0.309 ns) 1.146 ns counter24:HOUR_CONTROL\|Add1~61 3 COMB LCCOMB_X14_Y9_N0 2 " "Info: 3: + IC(0.215 ns) + CELL(0.309 ns) = 1.146 ns; Loc. = LCCOMB_X14_Y9_N0; Fanout = 2; COMB Node = 'counter24:HOUR_CONTROL\|Add1~61'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.524 ns" { counter24:HOUR_CONTROL|Equal0~26 counter24:HOUR_CONTROL|Add1~61 } "NODE_NAME" } } { "d:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.125 ns) 1.271 ns counter24:HOUR_CONTROL\|Add1~64 4 COMB LCCOMB_X14_Y9_N2 1 " "Info: 4: + IC(0.000 ns) + CELL(0.125 ns) = 1.271 ns; Loc. = LCCOMB_X14_Y9_N2; Fanout = 1; COMB Node = 'counter24:HOUR_CONTROL\|Add1~64'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.125 ns" { counter24:HOUR_CONTROL|Add1~61 counter24:HOUR_CONTROL|Add1~64 } "NODE_NAME" } } { "d:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.390 ns) + CELL(0.053 ns) 1.714 ns counter24:HOUR_CONTROL\|HIGH_REG~284 5 COMB LCCOMB_X14_Y9_N22 1 " "Info: 5: + IC(0.390 ns) + CELL(0.053 ns) = 1.714 ns; Loc. = LCCOMB_X14_Y9_N22; Fanout = 1; COMB Node = 'counter24:HOUR_CONTROL\|HIGH_REG~284'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.443 ns" { counter24:HOUR_CONTROL|Add1~64 counter24:HOUR_CONTROL|HIGH_REG~284 } "NODE_NAME" } } { "counter24.vhd" "" { Text "F:/clock/counter24.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 1.869 ns counter24:HOUR_CONTROL\|HIGH_REG\[1\] 6 REG LCFF_X14_Y9_N23 10 " "Info: 6: + IC(0.000 ns) + CELL(0.155 ns) = 1.869 ns; Loc. = LCFF_X14_Y9_N23; Fanout = 10; REG Node = 'counter24:HOUR_CONTROL\|HIGH_REG\[1\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { counter24:HOUR_CONTROL|HIGH_REG~284 counter24:HOUR_CONTROL|HIGH_REG[1] } "NODE_NAME" } } { "counter24.vhd" "" { Text "F:/clock/counter24.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.988 ns ( 52.86 % ) " "Info: Total cell delay = 0.988 ns ( 52.86 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.881 ns ( 47.14 % ) " "Info: Total interconnect delay = 0.881 ns ( 47.14 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.869 ns" { counter24:HOUR_CONTROL|LOW_REG[2] counter24:HOUR_CONTROL|Equal0~26 counter24:HOUR_CONTROL|Add1~61 counter24:HOUR_CONTROL|Add1~64 counter24:HOUR_CONTROL|HIGH_REG~284 counter24:HOUR_CONTROL|HIGH_REG[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.869 ns" { counter24:HOUR_CONTROL|LOW_REG[2] counter24:HOUR_CONTROL|Equal0~26 counter24:HOUR_CONTROL|Add1~61 counter24:HOUR_CONTROL|Add1~64 counter24:HOUR_CONTROL|HIGH_REG~284 counter24:HOUR_CONTROL|HIGH_REG[1] } { 0.000ns 0.276ns 0.215ns 0.000ns 0.390ns 0.000ns } { 0.000ns 0.346ns 0.309ns 0.125ns 0.053ns 0.155ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.182 ns - Smallest " "Info: - Smallest clock skew is -0.182 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "MODE destination 5.437 ns + Shortest register " "Info: + Shortest clock path from clock \"MODE\" to destination register is 5.437 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns MODE 1 CLK PIN_M2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M2; Fanout = 2; CLK Node = 'MODE'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { MODE } "NODE_NAME" } } { "top.vhd" "" { Text "F:/clock/top.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.574 ns) + CELL(0.712 ns) 2.150 ns adjuster:ADJUST_CONTROL\|CON\[1\] 2 REG LCFF_X39_Y16_N21 3 " "Info: 2: + IC(0.574 ns) + CELL(0.712 ns) = 2.150 ns; Loc. = LCFF_X39_Y16_N21; Fanout = 3; REG Node = 'adjuster:ADJUST_CONTROL\|CON\[1\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.286 ns" { MODE adjuster:ADJUST_CONTROL|CON[1] } "NODE_NAME" } } { "adjuster.vhd" "" { Text "F:/clock/adjuster.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.207 ns) + CELL(0.053 ns) 2.410 ns adjuster:ADJUST_CONTROL\|Mux0~5 3 COMB LCCOMB_X39_Y16_N22 1 " "Info: 3: + IC(0.207 ns) + CELL(0.053 ns) = 2.410 ns; Loc. = LCCOMB_X39_Y16_N22; Fanout = 1; COMB Node = 'adjuster:ADJUST_CONTROL\|Mux0~5'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.260 ns" { adjuster:ADJUST_CONTROL|CON[1] adjuster:ADJUST_CONTROL|Mux0~5 } "NODE_NAME" } } { "adjuster.vhd" "" { Text "F:/clock/adjuster.vhd" 42 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.204 ns) + CELL(0.154 ns) 2.768 ns adjuster:ADJUST_CONTROL\|CLK 4 COMB LCCOMB_X39_Y16_N8 1 " "Info: 4: + IC(0.204 ns) + CELL(0.154 ns) = 2.768 ns; Loc. = LCCOMB_X39_Y16_N8; Fanout = 1; COMB Node = 'adjuster:ADJUST_CONTROL\|CLK'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.358 ns" { adjuster:ADJUST_CONTROL|Mux0~5 adjuster:ADJUST_CONTROL|CLK } "NODE_NAME" } } { "adjuster.vhd" "" { Text "F:/clock/adjuster.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.385 ns) + CELL(0.000 ns) 4.153 ns adjuster:ADJUST_CONTROL\|CLK~clkctrl 5 COMB CLKCTRL_G11 8 " "Info: 5: + IC(1.385 ns) + CELL(0.000 ns) = 4.153 ns; Loc. = CLKCTRL_G11; Fanout = 8; COMB Node = 'adjuster:ADJUST_CONTROL\|CLK~clkctrl'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.385 ns" { adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl } "NODE_NAME" } } { "adjuster.vhd" "" { Text "F:/clock/adjuster.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.666 ns) + CELL(0.618 ns) 5.437 ns counter24:HOUR_CONTROL\|HIGH_REG\[1\] 6 REG LCFF_X14_Y9_N23 10 " "Info: 6: + IC(0.666 ns) + CELL(0.618 ns) = 5.437 ns; Loc. = LCFF_X14_Y9_N23; Fanout = 10; REG Node = 'counter24:HOUR_CONTROL\|HIGH_REG\[1\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.284 ns" { adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|HIGH_REG[1] } "NODE_NAME" } } { "counter24.vhd" "" { Text "F:/clock/counter24.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.401 ns ( 44.16 % ) " "Info: Total cell delay = 2.401 ns ( 44.16 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.036 ns ( 55.84 % ) " "Info: Total interconnect delay = 3.036 ns ( 55.84 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.437 ns" { MODE adjuster:ADJUST_CONTROL|CON[1] adjuster:ADJUST_CONTROL|Mux0~5 adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|HIGH_REG[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.437 ns" { MODE MODE~combout adjuster:ADJUST_CONTROL|CON[1] adjuster:ADJUST_CONTROL|Mux0~5 adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|HIGH_REG[1] } { 0.000ns 0.000ns 0.574ns 0.207ns 0.204ns 1.385ns 0.666ns } { 0.000ns 0.864ns 0.712ns 0.053ns 0.154ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "MODE source 5.619 ns - Longest register " "Info: - Longest clock path from clock \"MODE\" to source register is 5.619 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns MODE 1 CLK PIN_M2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M2; Fanout = 2; CLK Node = 'MODE'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { MODE } "NODE_NAME" } } { "top.vhd" "" { Text "F:/clock/top.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.574 ns) + CELL(0.712 ns) 2.150 ns adjuster:ADJUST_CONTROL\|CON\[0\] 2 REG LCFF_X39_Y16_N19 4 " "Info: 2: + IC(0.574 ns) + CELL(0.712 ns) = 2.150 ns; Loc. = LCFF_X39_Y16_N19; Fanout = 4; REG Node = 'adjuster:ADJUST_CONTROL\|CON\[0\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.286 ns" { MODE adjuster:ADJUST_CONTROL|CON[0] } "NODE_NAME" } } { "adjuster.vhd" "" { Text "F:/clock/adjuster.vhd" 30 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.217 ns) + CELL(0.225 ns) 2.592 ns adjuster:ADJUST_CONTROL\|Mux0~5 3 COMB LCCOMB_X39_Y16_N22 1 " "Info: 3: + IC(0.217 ns) + CELL(0.225 ns) = 2.592 ns; Loc. = LCCOMB_X39_Y16_N22; Fanout = 1; COMB Node = 'adjuster:ADJUST_CONTROL\|Mux0~5'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.442 ns" { adjuster:ADJUST_CONTROL|CON[0] adjuster:ADJUST_CONTROL|Mux0~5 } "NODE_NAME" } } { "adjuster.vhd" "" { Text "F:/clock/adjuster.vhd" 42 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.204 ns) + CELL(0.154 ns) 2.950 ns adjuster:ADJUST_CONTROL\|CLK 4 COMB LCCOMB_X39_Y16_N8 1 " "Info: 4: + IC(0.204 ns) + CELL(0.154 ns) = 2.950 ns; Loc. = LCCOMB_X39_Y16_N8; Fanout = 1; COMB Node = 'adjuster:ADJUST_CONTROL\|CLK'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.358 ns" { adjuster:ADJUST_CONTROL|Mux0~5 adjuster:ADJUST_CONTROL|CLK } "NODE_NAME" } } { "adjuster.vhd" "" { Text "F:/clock/adjuster.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.385 ns) + CELL(0.000 ns) 4.335 ns adjuster:ADJUST_CONTROL\|CLK~clkctrl 5 COMB CLKCTRL_G11 8 " "Info: 5: + IC(1.385 ns) + CELL(0.000 ns) = 4.335 ns; Loc. = CLKCTRL_G11; Fanout = 8; COMB Node = 'adjuster:ADJUST_CONTROL\|CLK~clkctrl'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.385 ns" { adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl } "NODE_NAME" } } { "adjuster.vhd" "" { Text "F:/clock/adjuster.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.666 ns) + CELL(0.618 ns) 5.619 ns counter24:HOUR_CONTROL\|LOW_REG\[2\] 6 REG LCFF_X14_Y9_N15 11 " "Info: 6: + IC(0.666 ns) + CELL(0.618 ns) = 5.619 ns; Loc. = LCFF_X14_Y9_N15; Fanout = 11; REG Node = 'counter24:HOUR_CONTROL\|LOW_REG\[2\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.284 ns" { adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|LOW_REG[2] } "NODE_NAME" } } { "counter24.vhd" "" { Text "F:/clock/counter24.vhd" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.573 ns ( 45.79 % ) " "Info: Total cell delay = 2.573 ns ( 45.79 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.046 ns ( 54.21 % ) " "Info: Total interconnect delay = 3.046 ns ( 54.21 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.619 ns" { MODE adjuster:ADJUST_CONTROL|CON[0] adjuster:ADJUST_CONTROL|Mux0~5 adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|LOW_REG[2] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.619 ns" { MODE MODE~combout adjuster:ADJUST_CONTROL|CON[0] adjuster:ADJUST_CONTROL|Mux0~5 adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|LOW_REG[2] } { 0.000ns 0.000ns 0.574ns 0.217ns 0.204ns 1.385ns 0.666ns } { 0.000ns 0.864ns 0.712ns 0.225ns 0.154ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.437 ns" { MODE adjuster:ADJUST_CONTROL|CON[1] adjuster:ADJUST_CONTROL|Mux0~5 adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|HIGH_REG[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.437 ns" { MODE MODE~combout adjuster:ADJUST_CONTROL|CON[1] adjuster:ADJUST_CONTROL|Mux0~5 adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|HIGH_REG[1] } { 0.000ns 0.000ns 0.574ns 0.207ns 0.204ns 1.385ns 0.666ns } { 0.000ns 0.864ns 0.712ns 0.053ns 0.154ns 0.000ns 0.618ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.619 ns" { MODE adjuster:ADJUST_CONTROL|CON[0] adjuster:ADJUST_CONTROL|Mux0~5 adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|LOW_REG[2] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.619 ns" { MODE MODE~combout adjuster:ADJUST_CONTROL|CON[0] adjuster:ADJUST_CONTROL|Mux0~5 adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|LOW_REG[2] } { 0.000ns 0.000ns 0.574ns 0.217ns 0.204ns 1.385ns 0.666ns } { 0.000ns 0.864ns 0.712ns 0.225ns 0.154ns 0.000ns 0.618ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" { } { { "counter24.vhd" "" { Text "F:/clock/counter24.vhd" 23 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" { } { { "counter24.vhd" "" { Text "F:/clock/counter24.vhd" 37 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.869 ns" { counter24:HOUR_CONTROL|LOW_REG[2] counter24:HOUR_CONTROL|Equal0~26 counter24:HOUR_CONTROL|Add1~61 counter24:HOUR_CONTROL|Add1~64 counter24:HOUR_CONTROL|HIGH_REG~284 counter24:HOUR_CONTROL|HIGH_REG[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.869 ns" { counter24:HOUR_CONTROL|LOW_REG[2] counter24:HOUR_CONTROL|Equal0~26 counter24:HOUR_CONTROL|Add1~61 counter24:HOUR_CONTROL|Add1~64 counter24:HOUR_CONTROL|HIGH_REG~284 counter24:HOUR_CONTROL|HIGH_REG[1] } { 0.000ns 0.276ns 0.215ns 0.000ns 0.390ns 0.000ns } { 0.000ns 0.346ns 0.309ns 0.125ns 0.053ns 0.155ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.437 ns" { MODE adjuster:ADJUST_CONTROL|CON[1] adjuster:ADJUST_CONTROL|Mux0~5 adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|HIGH_REG[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.437 ns" { MODE MODE~combout adjuster:ADJUST_CONTROL|CON[1] adjuster:ADJUST_CONTROL|Mux0~5 adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|HIGH_REG[1] } { 0.000ns 0.000ns 0.574ns 0.207ns 0.204ns 1.385ns 0.666ns } { 0.000ns 0.864ns 0.712ns 0.053ns 0.154ns 0.000ns 0.618ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.619 ns" { MODE adjuster:ADJUST_CONTROL|CON[0] adjuster:ADJUST_CONTROL|Mux0~5 adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|LOW_REG[2] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.619 ns" { MODE MODE~combout adjuster:ADJUST_CONTROL|CON[0] adjuster:ADJUST_CONTROL|Mux0~5 adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|LOW_REG[2] } { 0.000ns 0.000ns 0.574ns 0.217ns 0.204ns 1.385ns 0.666ns } { 0.000ns 0.864ns 0.712ns 0.225ns 0.154ns 0.000ns 0.618ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SET register counter24:HOUR_CONTROL\|LOW_REG\[2\] register counter24:HOUR_CONTROL\|HIGH_REG\[1\] 487.09 MHz 2.053 ns Internal " "Info: Clock \"SET\" has Internal fmax of 487.09 MHz between source register \"counter24:HOUR_CONTROL\|LOW_REG\[2\]\" and destination register \"counter24:HOUR_CONTROL\|HIGH_REG\[1\]\" (period= 2.053 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.869 ns + Longest register register " "Info: + Longest register to register delay is 1.869 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter24:HOUR_CONTROL\|LOW_REG\[2\] 1 REG LCFF_X14_Y9_N15 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y9_N15; Fanout = 11; REG Node = 'counter24:HOUR_CONTROL\|LOW_REG\[2\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { counter24:HOUR_CONTROL|LOW_REG[2] } "NODE_NAME" } } { "counter24.vhd" "" { Text "F:/clock/counter24.vhd" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.276 ns) + CELL(0.346 ns) 0.622 ns counter24:HOUR_CONTROL\|Equal0~26 2 COMB LCCOMB_X14_Y9_N20 3 " "Info: 2: + IC(0.276 ns) + CELL(0.346 ns) = 0.622 ns; Loc. = LCCOMB_X14_Y9_N20; Fanout = 3; COMB Node = 'counter24:HOUR_CONTROL\|Equal0~26'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.622 ns" { counter24:HOUR_CONTROL|LOW_REG[2] counter24:HOUR_CONTROL|Equal0~26 } "NODE_NAME" } } { "d:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.215 ns) + CELL(0.309 ns) 1.146 ns counter24:HOUR_CONTROL\|Add1~61 3 COMB LCCOMB_X14_Y9_N0 2 " "Info: 3: + IC(0.215 ns) + CELL(0.309 ns) = 1.146 ns; Loc. = LCCOMB_X14_Y9_N0; Fanout = 2; COMB Node = 'counter24:HOUR_CONTROL\|Add1~61'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.524 ns" { counter24:HOUR_CONTROL|Equal0~26 counter24:HOUR_CONTROL|Add1~61 } "NODE_NAME" } } { "d:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.125 ns) 1.271 ns counter24:HOUR_CONTROL\|Add1~64 4 COMB LCCOMB_X14_Y9_N2 1 " "Info: 4: + IC(0.000 ns) + CELL(0.125 ns) = 1.271 ns; Loc. = LCCOMB_X14_Y9_N2; Fanout = 1; COMB Node = 'counter24:HOUR_CONTROL\|Add1~64'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.125 ns" { counter24:HOUR_CONTROL|Add1~61 counter24:HOUR_CONTROL|Add1~64 } "NODE_NAME" } } { "d:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.390 ns) + CELL(0.053 ns) 1.714 ns counter24:HOUR_CONTROL\|HIGH_REG~284 5 COMB LCCOMB_X14_Y9_N22 1 " "Info: 5: + IC(0.390 ns) + CELL(0.053 ns) = 1.714 ns; Loc. = LCCOMB_X14_Y9_N22; Fanout = 1; COMB Node = 'counter24:HOUR_CONTROL\|HIGH_REG~284'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.443 ns" { counter24:HOUR_CONTROL|Add1~64 counter24:HOUR_CONTROL|HIGH_REG~284 } "NODE_NAME" } } { "counter24.vhd" "" { Text "F:/clock/counter24.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 1.869 ns counter24:HOUR_CONTROL\|HIGH_REG\[1\] 6 REG LCFF_X14_Y9_N23 10 " "Info: 6: + IC(0.000 ns) + CELL(0.155 ns) = 1.869 ns; Loc. = LCFF_X14_Y9_N23; Fanout = 10; REG Node = 'counter24:HOUR_CONTROL\|HIGH_REG\[1\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { counter24:HOUR_CONTROL|HIGH_REG~284 counter24:HOUR_CONTROL|HIGH_REG[1] } "NODE_NAME" } } { "counter24.vhd" "" { Text "F:/clock/counter24.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.988 ns ( 52.86 % ) " "Info: Total cell delay = 0.988 ns ( 52.86 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.881 ns ( 47.14 % ) " "Info: Total interconnect delay = 0.881 ns ( 47.14 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.869 ns" { counter24:HOUR_CONTROL|LOW_REG[2] counter24:HOUR_CONTROL|Equal0~26 counter24:HOUR_CONTROL|Add1~61 counter24:HOUR_CONTROL|Add1~64 counter24:HOUR_CONTROL|HIGH_REG~284 counter24:HOUR_CONTROL|HIGH_REG[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.869 ns" { counter24:HOUR_CONTROL|LOW_REG[2] counter24:HOUR_CONTROL|Equal0~26 counter24:HOUR_CONTROL|Add1~61 counter24:HOUR_CONTROL|Add1~64 counter24:HOUR_CONTROL|HIGH_REG~284 counter24:HOUR_CONTROL|HIGH_REG[1] } { 0.000ns 0.276ns 0.215ns 0.000ns 0.390ns 0.000ns } { 0.000ns 0.346ns 0.309ns 0.125ns 0.053ns 0.155ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SET destination 4.417 ns + Shortest register " "Info: + Shortest clock path from clock \"SET\" to destination register is 4.417 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns SET 1 CLK PIN_M3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M3; Fanout = 1; CLK Node = 'SET'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SET } "NODE_NAME" } } { "top.vhd" "" { Text "F:/clock/top.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.612 ns) + CELL(0.272 ns) 1.748 ns adjuster:ADJUST_CONTROL\|CLK 2 COMB LCCOMB_X39_Y16_N8 1 " "Info: 2: + IC(0.612 ns) + CELL(0.272 ns) = 1.748 ns; Loc. = LCCOMB_X39_Y16_N8; Fanout = 1; COMB Node = 'adjuster:ADJUST_CONTROL\|CLK'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.884 ns" { SET adjuster:ADJUST_CONTROL|CLK } "NODE_NAME" } } { "adjuster.vhd" "" { Text "F:/clock/adjuster.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.385 ns) + CELL(0.000 ns) 3.133 ns adjuster:ADJUST_CONTROL\|CLK~clkctrl 3 COMB CLKCTRL_G11 8 " "Info: 3: + IC(1.385 ns) + CELL(0.000 ns) = 3.133 ns; Loc. = CLKCTRL_G11; Fanout = 8; COMB Node = 'adjuster:ADJUST_CONTROL\|CLK~clkctrl'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.385 ns" { adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl } "NODE_NAME" } } { "adjuster.vhd" "" { Text "F:/clock/adjuster.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.666 ns) + CELL(0.618 ns) 4.417 ns counter24:HOUR_CONTROL\|HIGH_REG\[1\] 4 REG LCFF_X14_Y9_N23 10 " "Info: 4: + IC(0.666 ns) + CELL(0.618 ns) = 4.417 ns; Loc. = LCFF_X14_Y9_N23; Fanout = 10; REG Node = 'counter24:HOUR_CONTROL\|HIGH_REG\[1\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.284 ns" { adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|HIGH_REG[1] } "NODE_NAME" } } { "counter24.vhd" "" { Text "F:/clock/counter24.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.754 ns ( 39.71 % ) " "Info: Total cell delay = 1.754 ns ( 39.71 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.663 ns ( 60.29 % ) " "Info: Total interconnect delay = 2.663 ns ( 60.29 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.417 ns" { SET adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|HIGH_REG[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.417 ns" { SET SET~combout adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|HIGH_REG[1] } { 0.000ns 0.000ns 0.612ns 1.385ns 0.666ns } { 0.000ns 0.864ns 0.272ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SET source 4.417 ns - Longest register " "Info: - Longest clock path from clock \"SET\" to source register is 4.417 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns SET 1 CLK PIN_M3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M3; Fanout = 1; CLK Node = 'SET'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { SET } "NODE_NAME" } } { "top.vhd" "" { Text "F:/clock/top.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.612 ns) + CELL(0.272 ns) 1.748 ns adjuster:ADJUST_CONTROL\|CLK 2 COMB LCCOMB_X39_Y16_N8 1 " "Info: 2: + IC(0.612 ns) + CELL(0.272 ns) = 1.748 ns; Loc. = LCCOMB_X39_Y16_N8; Fanout = 1; COMB Node = 'adjuster:ADJUST_CONTROL\|CLK'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.884 ns" { SET adjuster:ADJUST_CONTROL|CLK } "NODE_NAME" } } { "adjuster.vhd" "" { Text "F:/clock/adjuster.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.385 ns) + CELL(0.000 ns) 3.133 ns adjuster:ADJUST_CONTROL\|CLK~clkctrl 3 COMB CLKCTRL_G11 8 " "Info: 3: + IC(1.385 ns) + CELL(0.000 ns) = 3.133 ns; Loc. = CLKCTRL_G11; Fanout = 8; COMB Node = 'adjuster:ADJUST_CONTROL\|CLK~clkctrl'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.385 ns" { adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl } "NODE_NAME" } } { "adjuster.vhd" "" { Text "F:/clock/adjuster.vhd" 14 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.666 ns) + CELL(0.618 ns) 4.417 ns counter24:HOUR_CONTROL\|LOW_REG\[2\] 4 REG LCFF_X14_Y9_N15 11 " "Info: 4: + IC(0.666 ns) + CELL(0.618 ns) = 4.417 ns; Loc. = LCFF_X14_Y9_N15; Fanout = 11; REG Node = 'counter24:HOUR_CONTROL\|LOW_REG\[2\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.284 ns" { adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|LOW_REG[2] } "NODE_NAME" } } { "counter24.vhd" "" { Text "F:/clock/counter24.vhd" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.754 ns ( 39.71 % ) " "Info: Total cell delay = 1.754 ns ( 39.71 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.663 ns ( 60.29 % ) " "Info: Total interconnect delay = 2.663 ns ( 60.29 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.417 ns" { SET adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|LOW_REG[2] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.417 ns" { SET SET~combout adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|LOW_REG[2] } { 0.000ns 0.000ns 0.612ns 1.385ns 0.666ns } { 0.000ns 0.864ns 0.272ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.417 ns" { SET adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|HIGH_REG[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.417 ns" { SET SET~combout adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|HIGH_REG[1] } { 0.000ns 0.000ns 0.612ns 1.385ns 0.666ns } { 0.000ns 0.864ns 0.272ns 0.000ns 0.618ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.417 ns" { SET adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|LOW_REG[2] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.417 ns" { SET SET~combout adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|LOW_REG[2] } { 0.000ns 0.000ns 0.612ns 1.385ns 0.666ns } { 0.000ns 0.864ns 0.272ns 0.000ns 0.618ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" { } { { "counter24.vhd" "" { Text "F:/clock/counter24.vhd" 23 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" { } { { "counter24.vhd" "" { Text "F:/clock/counter24.vhd" 37 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.869 ns" { counter24:HOUR_CONTROL|LOW_REG[2] counter24:HOUR_CONTROL|Equal0~26 counter24:HOUR_CONTROL|Add1~61 counter24:HOUR_CONTROL|Add1~64 counter24:HOUR_CONTROL|HIGH_REG~284 counter24:HOUR_CONTROL|HIGH_REG[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.869 ns" { counter24:HOUR_CONTROL|LOW_REG[2] counter24:HOUR_CONTROL|Equal0~26 counter24:HOUR_CONTROL|Add1~61 counter24:HOUR_CONTROL|Add1~64 counter24:HOUR_CONTROL|HIGH_REG~284 counter24:HOUR_CONTROL|HIGH_REG[1] } { 0.000ns 0.276ns 0.215ns 0.000ns 0.390ns 0.000ns } { 0.000ns 0.346ns 0.309ns 0.125ns 0.053ns 0.155ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.417 ns" { SET adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|HIGH_REG[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.417 ns" { SET SET~combout adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|HIGH_REG[1] } { 0.000ns 0.000ns 0.612ns 1.385ns 0.666ns } { 0.000ns 0.864ns 0.272ns 0.000ns 0.618ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.417 ns" { SET adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|LOW_REG[2] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.417 ns" { SET SET~combout adjuster:ADJUST_CONTROL|CLK adjuster:ADJUST_CONTROL|CLK~clkctrl counter24:HOUR_CONTROL|LOW_REG[2] } { 0.000ns 0.000ns 0.612ns 1.385ns 0.666ns } { 0.000ns 0.864ns 0.272ns 0.000ns 0.618ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
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