timer.map.qmsg

多功能计时器,具有校准

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Sep 27 19:31:31 2008 " "Info: Processing started: Sat Sep 27 19:31:31 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off timer -c timer " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off timer -c timer" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file top.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 timer-rtl " "Info: Found design unit 1: timer-rtl" {  } { { "top.vhd" "" { Text "F:/clock/top.vhd" 19 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 timer " "Info: Found entity 1: timer" {  } { { "top.vhd" "" { Text "F:/clock/top.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter60.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file counter60.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter60-rtl " "Info: Found design unit 1: counter60-rtl" {  } { { "counter60.vhd" "" { Text "F:/clock/counter60.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 counter60 " "Info: Found entity 1: counter60" {  } { { "counter60.vhd" "" { Text "F:/clock/counter60.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter24.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file counter24.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter24-rtl " "Info: Found design unit 1: counter24-rtl" {  } { { "counter24.vhd" "" { Text "F:/clock/counter24.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 counter24 " "Info: Found entity 1: counter24" {  } { { "counter24.vhd" "" { Text "F:/clock/counter24.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "adjuster.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file adjuster.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 adjuster-rtl " "Info: Found design unit 1: adjuster-rtl" {  } { { "adjuster.vhd" "" { Text "F:/clock/adjuster.vhd" 21 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 adjuster " "Info: Found entity 1: adjuster" {  } { { "adjuster.vhd" "" { Text "F:/clock/adjuster.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "display.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file display.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 display-rtl " "Info: Found design unit 1: display-rtl" {  } { { "display.vhd" "" { Text "F:/clock/display.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 display " "Info: Found entity 1: display" {  } { { "display.vhd" "" { Text "F:/clock/display.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "timer " "Info: Elaborating entity \"timer\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "adjuster adjuster:ADJUST_CONTROL " "Info: Elaborating entity \"adjuster\" for hierarchy \"adjuster:ADJUST_CONTROL\"" {  } { { "top.vhd" "ADJUST_CONTROL" { Text "F:/clock/top.vhd" 76 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "SCE_REG adjuster.vhd(70) " "Warning (10492): VHDL Process Statement warning at adjuster.vhd(70): signal \"SCE_REG\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "adjuster.vhd" "" { Text "F:/clock/adjuster.vhd" 70 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "MCE_REG adjuster.vhd(71) " "Warning (10492): VHDL Process Statement warning at adjuster.vhd(71): signal \"MCE_REG\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "adjuster.vhd" "" { Text "F:/clock/adjuster.vhd" 71 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "HCE_REG adjuster.vhd(72) " "Warning (10492): VHDL Process Statement warning at adjuster.vhd(72): signal \"HCE_REG\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "adjuster.vhd" "" { Text "F:/clock/adjuster.vhd" 72 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "SET adjuster.vhd(73) " "Warning (10492): VHDL Process Statement warning at adjuster.vhd(73): signal \"SET\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "adjuster.vhd" "" { Text "F:/clock/adjuster.vhd" 73 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "EN adjuster.vhd(74) " "Warning (10492): VHDL Process Statement warning at adjuster.vhd(74): signal \"EN\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "adjuster.vhd" "" { Text "F:/clock/adjuster.vhd" 74 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "S_ENOUT adjuster.vhd(75) " "Warning (10492): VHDL Process Statement warning at adjuster.vhd(75): signal \"S_ENOUT\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "adjuster.vhd" "" { Text "F:/clock/adjuster.vhd" 75 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "M_ENOUT adjuster.vhd(76) " "Warning (10492): VHDL Process Statement warning at adjuster.vhd(76): signal \"M_ENOUT\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "adjuster.vhd" "" { Text "F:/clock/adjuster.vhd" 76 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CLK1HZ adjuster.vhd(77) " "Warning (10492): VHDL Process Statement warning at adjuster.vhd(77): signal \"CLK1HZ\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "adjuster.vhd" "" { Text "F:/clock/adjuster.vhd" 77 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}