timer.fit.summary

来自「多功能计时器,具有校准」· SUMMARY 代码 · 共 18 行

Fitter Status : Successful - Mon Aug 18 11:40:25 2008
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Full Version
Revision Name : timer
Top-level Entity Name : timer
Family : Stratix II
Device : EP2S15F484C3
Timing Models : Final
Logic utilization : < 1 %
    Combinational ALUTs : 31 / 12,480 ( < 1 % )
    Dedicated logic registers : 10 / 12,480 ( < 1 % )
Total registers : 10
Total pins : 45 / 343 ( 13 % )
Total virtual pins : 0
Total block memory bits : 0 / 419,328 ( 0 % )
DSP block 9-bit elements : 0 / 96 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )