counter60.vhd

来自「多功能计时器,具有校准」· VHDL 代码 · 共 38 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY counter60 IS
PORT(
     CLK1HZ : IN        STD_LOGIC;
     EN      : IN       STD_LOGIC;
     ENOUT   : OUT      STD_LOGIC;
     LOW     : OUT      STD_LOGIC_VECTOR(3 DOWNTO 0);
     HIGH    : OUT      STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END counter60;

ARCHITECTURE rtl of counter60 IS
SIGNAL LOW_REG :STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
SIGNAL HIGH_REG :STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
BEGIN
LOW_PROC: PROCESS(CLK1HZ,EN)
BEGIN
   IF rising_edge(CLK1HZ) THEN
     IF EN='1'  THEN
       IF LOW_REG="1001" THEN
         IF HIGH_REG="1001" THEN
            HIGH_REG<="0000";
         ELSE 
HIGH_REG<=HIGH_REG+'1';
END IF;
END IF;
END IF;
END IF;
END PROCESS;

HIGH<=HIGH_REG;
ENOUT<='1'WHEN LOW_REG="1001" AND HIGH_REG="0101" ELSE
'0';
END rtl;