timer.map.summary

来自「多功能计时器,具有校准」· SUMMARY 代码 · 共 16 行

Analysis & Synthesis Status : Successful - Sat Sep 27 19:31:34 2008
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Full Version
Revision Name : timer
Top-level Entity Name : timer
Family : Stratix II
Logic utilization : N/A
    Combinational ALUTs : 31
    Dedicated logic registers : 10
Total registers : 10
Total pins : 45
Total virtual pins : 0
Total block memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0