zong2.vhd

来自「基于QuartusII环境下以模块化的形式做成的视频复合同步信号。」· VHDL 代码 · 共 48 行

library ieee;
use ieee.std_logic_1164.all;

entity zong2 is
port(
	ck:		in std_logic;
	htb,cmc,jh:	out std_logic
	);
end zong2;

architecture a of zong2 is

signal count: integer range 0 to 79;
begin
process
	begin
		wait until ck= '1';
		if count < 79 then
			count <= count + 1;
		else
			count <= 0;
		end if;
	end process;
process(count)
	begin
	    if count <=5 then
			htb <= '0';
	    else
	        htb<='1';
		end if;
	end process;
process(count)
	begin
	    if count <=2 then
			jh <= '0';
	    else
	        jh<='1';
		end if;
	end process;
process(count)
	begin
	    if count <=33 then
			cmc <= '0';
	    else
	        cmc<='1';
		end if;
	end process;
	end a;