changtb.vhd

来自「基于QuartusII环境下以模块化的形式做成的视频复合同步信号。」· VHDL 代码 · 共 32 行

library ieee;
use ieee.std_logic_1164.all;

entity changtb is
port(
	ck:		in std_logic;
	ctb:	out std_logic
	);
end changtb;

architecture a of changtb is

signal count: integer range 0 to 24999;
begin
process
	begin
		wait until ck = '1' ;
		if count < 24999 then
			count <= count + 1;
		else
			count <= 0;
		end if;
	end process;
process(count)
	begin
	    if count <=199 then
			ctb <= '0';
	    else
	        ctb<='1';
		end if;
	end process;
	end a;