📄 guolv.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity guolv is
port(
ck,newresult: in std_logic;
s: out std_logic
);
end guolv;
architecture a of guolv is
signal count: integer range 0 to 50000;
begin
process
begin
if ck'event and ck='1' then
s<=newresult;
end if;
end process;
end a;
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