zong.vhd

基于QuartusII环境下以模块化的形式做成的视频复合同步信号。

library ieee;
use ieee.std_logic_1164.all;

entity zong is
port(
	ck:		in std_logic;
	newresult:	out std_logic
	);
end zong;

architecture a of zong is

signal count: integer range 0 to 79;
signal count1: integer range 0 to 49999;
signal htb,jh,cmc,s:std_logic;
begin
process
	begin
		wait until ck= '1';
		if count < 79 then
			count <= count + 1;
		else
			count <= 0;
		end if;
	end process;
process(count)
	begin
	    if count <=5 then
			htb <= '0';
	    else
	        htb<='1';
		end if;
	end process;
process(count)
	begin
	    if count <=2 then
			jh <= '0';
	 elsif count>2 and count<=39 then
	        jh<='1';
	elsif count>39 and count<=42 then
	        jh <= '0';
	else jh<='1';
		end if;
	end process;
process(count)
	begin
	    if count <=33 then
			cmc <= '0';
	    elsif count>33 and count<=39 then
	        cmc<='1';
	    elsif count>39 and count<=73 then
	        cmc<='0';
	    else cmc<='1';
		end if;
	end process;
	

process
	begin
		wait until ck= '1';
		if count1 < 49999 then
			count1 <= count1 + 1;
		else
			count1 <= 0;
		end if;
	end process;
	
	
process(count1)
	begin
	    if count1 <=199 then
			s<=cmc;
	    elsif count1<=399 and count1>=200 then
	       s<=jh;
	    elsif count1<=24799 and count1>=400 then
	       s<=htb;
	    elsif count1<=24999 and count1>=24800 then
	       s<=jh;
	    elsif count1<=25199 and count1>=25000 then
	       s<=cmc;
	    elsif count1<=25399 and count1>=25200 then
	       s<=jh;
	    elsif count1<=49800 and count1>=25400 then
	       s<=htb;
	    else 
	       s<=jh;
	  end if;
	end process;
process(ck)
	begin
		if ck'event and ck='1' then
	      newresult<=s;
		end if;
	end process;
end a;