tb2.vhd

来自「基于QuartusII环境下以模块化的形式做成的视频复合同步信号。」· VHDL 代码 · 共 45 行

library ieee;
use ieee.std_logic_1164.all;

entity tb2 is
port(
	ck,htb,cmc,jh:		in std_logic;
	newresult2:	out std_logic
	);
end tb2;

architecture a of tb2 is

signal count: integer range 0 to 50000;
begin
process
	begin
		wait until ck = '1' ;
		if count <50000  then
			count <= count + 1;
		else
			count <= 0;
		end if;
	end process;

process(count)
	begin
	    if count <=199 then
			newresult2<=cmc;
	    elsif count<=399 and count>=200 then
	       newresult2<=jh;
	    elsif count<=24799 and count>=400 then
	       newresult2<=htb;
	    elsif count<=24999 and count>=24800 then
	       newresult2<=jh;
	    elsif count<=25199 and count>=25000 then
	       newresult2<=cmc;
	    elsif count<=25399 and count>=25200 then
	       newresult2<=jh;
	    elsif count<=49800 and count>=25400 then
	       newresult2<=htb;
	    else 
	       newresult2<=jh;
	  end if;
	end process;
end a;