fhtb.sim.talkback.xml

基于QuartusII环境下以模块化的形式做成的视频复合同步信号。

<!--
This XML file (created on Mon Feb 18 18:58:40 2008) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to www.altera.com/products/software/download/dnl-download_license.html
-->
<talkback>
<ver>5.1</ver>
<schema>quartus_version_5.1_build_216.xsd</schema><license>
	<nic_id>001b7781afc8</nic_id>
	<cdrive_id>289cf6a4</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>5.1</version>
	<build>Build 216</build>
	<service_pack_label>2</service_pack_label>
	<binary_type>32</binary_type>
	<module>quartus_sim.exe</module>
	<edition>Web Edition</edition>
	<eval>Eval</eval>
	<compilation_end_time>Mon Feb 18 18:58:40 2008</compilation_end_time>
</tool>
<machine>
	<os>Unknown</os>
	<cpu>
		<proc_count>2</proc_count>
		<cpu_freq units="MHz">1799</cpu_freq>
	</cpu>
	<ram units="MB">2046</ram>
</machine>
<top_file>D:/视频同步信号合成/fhtb</top_file>
<compilation_summary>
	<flow_status>Successful - Mon Feb 18 18:58:40 2008</flow_status>
	<simulator_setting_name>fhtb</simulator_setting_name>
	<top_level_entity_name>fhtb</top_level_entity_name>
</compilation_summary>
<compile_id>772A1F69</compile_id>
<mep_data>
	<command_line>quartus_sim --read_settings_files=on --write_settings_files=off fhtb -c fhtb</command_line>
</mep_data>
<messages>
	<info>Info: Quartus II Simulator was successful. 0 errors, 0 warnings</info>
	<info>Info: Elapsed time: 00:01:34</info>
	<info>Info: Processing ended: Mon Feb 18 18:58:40 2008</info>
	<info>Info: Number of transitions in simulation is 1086333</info>
	<info>Info: Simulation coverage is      88.82 %</info>
</messages>
<simulator_settings>
	<row>
		<option>Simulation mode</option>
		<setting>Timing</setting>
		<default_value>Timing</default_value>
	</row>
	<row>
		<option>Start time</option>
		<setting units="ns">0</setting>
		<default_value units="ns">0</default_value>
	</row>
	<row>
		<option>Add pins automatically to simulation output waveforms</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Check outputs</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Report simulation coverage</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Detect setup and hold time violations</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Detect glitches</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Automatically save/load simulation netlist</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Disable timing delays in Timing Simulation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Generate Signal Activity File</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Group bus channels in simulation results</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Preserve fewer signal transitions to reduce memory requirements</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Overwrite Waveform Inputs With Simulation Outputs</option>
		<setting>On</setting>
	</row>
</simulator_settings>
<simulator_summary>
	<simulation_start_time>0 ps</simulation_start_time>
	<simulation_end_time>42.0 ms</simulation_end_time>
	<simulation_netlist_size>194 nodes</simulation_netlist_size>
	<simulation_coverage>     88.82 %</simulation_coverage>
	<total_number_of_transitions>1086333</total_number_of_transitions>
	<family>MAX7000AE</family>
	<device>EPM7256AEFC100-5</device>
</simulator_summary>
<compile_id>AFFF1A91</compile_id>
</talkback>