📄 fhtb.map.talkback.xml
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<!--
This XML file (created on Mon Feb 18 18:56:47 2008) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature. To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder. For more information, go
to www.altera.com/products/software/download/dnl-download_license.html
-->
<talkback>
<ver>5.1</ver>
<schema>quartus_version_5.1_build_216.xsd</schema><license>
<nic_id>001b7781afc8</nic_id>
<cdrive_id>289cf6a4</cdrive_id>
</license>
<tool>
<name>Quartus II</name>
<version>5.1</version>
<build>Build 216</build>
<service_pack_label>2</service_pack_label>
<binary_type>32</binary_type>
<module>quartus_map.exe</module>
<edition>Web Edition</edition>
<eval>Eval</eval>
<compilation_end_time>Mon Feb 18 18:56:47 2008</compilation_end_time>
</tool>
<machine>
<os>Unknown</os>
<cpu>
<proc_count>2</proc_count>
<cpu_freq units="MHz">1799</cpu_freq>
</cpu>
<ram units="MB">2046</ram>
</machine>
<top_file>D:/视频同步信号合成/fhtb</top_file>
<compilation_summary>
<flow_status>Successful - Mon Feb 18 18:56:47 2008</flow_status>
<quartus_ii_version>5.1 Build 216 03/06/2006 SP 2 SJ Web Edition</quartus_ii_version>
<revision_name>fhtb</revision_name>
<top_level_entity_name>fhtb</top_level_entity_name>
<family>MAX7000AE</family>
<device>EPM7256AEFC100-5</device>
<timing_models>Final</timing_models>
<met_timing_requirements>N/A</met_timing_requirements>
<total_macrocells>186</total_macrocells>
<total_pins>7</total_pins>
</compilation_summary>
<compile_id>55C27C2A</compile_id>
<mep_data>
<command_line>quartus_map --read_settings_files=on --write_settings_files=off fhtb -c fhtb</command_line>
</mep_data>
<software_data>
<smart_recompile>off</smart_recompile>
</software_data>
<messages>
<warning>Warning: Reduced register "junh:inst4|lpm_counter:count_rtl_3|dffs[6]" with stuck data_in port to stuck value GND</warning>
<warning>Warning: Reduced register "junh:inst4|lpm_counter:count_rtl_3|dffs[7]" with stuck data_in port to stuck value GND</warning>
<warning>Warning: Reduced register "chimc:inst3|lpm_counter:count_rtl_2|dffs[6]" with stuck data_in port to stuck value GND</warning>
<warning>Warning: Reduced register "chimc:inst3|lpm_counter:count_rtl_2|dffs[7]" with stuck data_in port to stuck value GND</warning>
<warning>Warning (10492): VHDL Process Statement warning at zong.vhd(86): signal "jh" is read inside the Process Statement but isn't in the Process Statement's sensivitity list</warning>
<info>Info: Quartus II Analysis & Synthesis was successful. 0 errors, 20 warnings</info>
<info>Info: Elapsed time: 00:00:07</info>
<info>Info: Processing ended: Mon Feb 18 18:56:47 2008</info>
<info>Info: Implemented 194 device resources after synthesis - the final resource count might be different</info>
<info>Info: Implemented 1 shareable expanders</info>
</messages>
<analysis___synthesis_settings>
<row>
<option>Device</option>
<setting>EPM7256AEFC100-5</setting>
</row>
<row>
<option>Top-level entity name</option>
<setting>fhtb</setting>
<default_value>fhtb</default_value>
</row>
<row>
<option>Family name</option>
<setting>MAX7000AE</setting>
<default_value>Stratix</default_value>
</row>
<row>
<option>Use smart compilation</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Create Debugging Nodes for IP Cores</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Preserve fewer node names</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Disable OpenCore Plus hardware evaluation</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Verilog Version</option>
<setting>Verilog_2001</setting>
<default_value>Verilog_2001</default_value>
</row>
<row>
<option>VHDL Version</option>
<setting>VHDL93</setting>
<default_value>VHDL93</default_value>
</row>
<row>
<option>State Machine Processing</option>
<setting>Auto</setting>
<default_value>Auto</default_value>
</row>
<row>
<option>Extract Verilog State Machines</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Extract VHDL State Machines</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Add Pass-Through Logic to Inferred RAMs</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>NOT Gate Push-Back</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Power-Up Don't Care</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Remove Redundant Logic Cells</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Remove Duplicate Registers</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Ignore CARRY Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore CASCADE Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore GLOBAL Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore ROW GLOBAL Buffers</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Ignore LCELL Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A</option>
<setting>Auto</setting>
<default_value>Auto</default_value>
</row>
<row>
<option>Ignore SOFT Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Limit AHDL Integers to 32 Bits</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Optimization Technique -- MAX 7000B/7000AE/3000A/7000S/7000A</option>
<setting>Speed</setting>
<default_value>Speed</default_value>
</row>
<row>
<option>Allow XOR Gate Usage</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto Logic Cell Insertion</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Parallel Expander Chain Length -- MAX 7000B/7000AE/3000A/7000S/7000A</option>
<setting>4</setting>
<default_value>4</default_value>
</row>
<row>
<option>Auto Parallel Expanders</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto Open-Drain Pins</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Remove Duplicate Logic</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>Auto Resource Sharing</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Maximum Fan-in Per Macrocell -- MAX 7000B/7000AE/3000A/7000S/7000A</option>
<setting>100</setting>
<default_value>100</default_value>
</row>
<row>
<option>Ignore translate_off and translate_on Synthesis Directives</option>
<setting>Off</setting>
<default_value>Off</default_value>
</row>
<row>
<option>Show Parameter Settings Tables in Synthesis Report</option>
<setting>On</setting>
<default_value>On</default_value>
</row>
<row>
<option>HDL message level</option>
<setting>Level2</setting>
<default_value>Level2</default_value>
</row>
</analysis___synthesis_settings>
</talkback>
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