fhtb.tan.talkback.xml

基于QuartusII环境下以模块化的形式做成的视频复合同步信号。

<!--
This XML file (created on Mon Feb 18 18:56:56 2008) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to www.altera.com/products/software/download/dnl-download_license.html
-->
<talkback>
<ver>5.1</ver>
<schema>quartus_version_5.1_build_216.xsd</schema><license>
	<nic_id>001b7781afc8</nic_id>
	<cdrive_id>289cf6a4</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>5.1</version>
	<build>Build 216</build>
	<service_pack_label>2</service_pack_label>
	<binary_type>32</binary_type>
	<module>quartus_tan.exe</module>
	<edition>Web Edition</edition>
	<eval>Eval</eval>
	<compilation_end_time>Mon Feb 18 18:56:56 2008</compilation_end_time>
</tool>
<machine>
	<os>Unknown</os>
	<cpu>
		<proc_count>2</proc_count>
		<cpu_freq units="MHz">1799</cpu_freq>
	</cpu>
	<ram units="MB">2046</ram>
</machine>
<top_file>D:/视频同步信号合成/fhtb</top_file>
<compilation_summary>
	<flow_status>Successful - Mon Feb 18 18:56:56 2008</flow_status>
	<quartus_ii_version>5.1 Build 216 03/06/2006 SP 2 SJ Web Edition</quartus_ii_version>
	<revision_name>fhtb</revision_name>
	<top_level_entity_name>fhtb</top_level_entity_name>
	<family>MAX7000AE</family>
	<device>EPM7256AEFC100-5</device>
	<timing_models>Final</timing_models>
	<met_timing_requirements>Yes</met_timing_requirements>
	<total_macrocells>186 / 256 ( 73 % )</total_macrocells>
	<total_pins>11 / 84 ( 13 % )</total_pins>
</compilation_summary>
<compile_id>863A9C0D</compile_id>
<mep_data>
	<command_line>quartus_tan --read_settings_files=off --write_settings_files=off fhtb -c fhtb</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<messages>
	<warning>Warning: Found pins functioning as undefined clocks and/or memory enables</warning>
	<warning>Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family</warning>
	<info>Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings</info>
	<info>Info: Elapsed time: 00:00:01</info>
	<info>Info: Processing ended: Mon Feb 18 18:56:56 2008</info>
	<info>Info: tco from clock &quot;ck&quot; to destination pin &quot;result&quot; through register &quot;tb:inst7|lpm_counter:count_rtl_4|dffs[13]&quot; is 12.900 ns</info>
	<info>Info: + Longest register to pin delay is 10.300 ns</info>
</messages>
<clock_settings_summary>
	<row>
		<clock_node_name>ck</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
</clock_settings_summary>
<performance>
	<nonclk>
		<type>Worst-case tco</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>12.900 ns</actual>
	</nonclk>
	<clk>
		<name>ck</name>
		<slack>N/A</slack>
		<required>None</required>
		<actual>147.06 MHz ( period = 6.800 ns )</actual>
	</clk>
</performance>
<compile_id>BF10332D</compile_id>
</talkback>