sum_rx.txt

来自「these files are written in verilog but i」· 文本 代码 · 共 8 行

`timescale 1ns/1ps
module sum_rx(q61_rx,q62_rx,gs_rx);
input q61_rx,q62_rx ;
output gs_rx;
 
 assign  gs_rx=q61_rx^q62_rx;
 
endmodule