ser2par.txt

来自「these files are written in verilog but i」· 文本 代码 · 共 10 行

`timescale 1ns/1ps
module ser_par_conv (dOut, clk1, data);
  output [7:0] dOut;
  input        clk1,   data;
  reg    [7:0] dOut;

  always @ (posedge clk1)
        dOut = {data, dOut[7:1]};

  endmodule