oneshot.txt

these files are written in verilog but i am uploading in text format

`timescale 1ns/1ps
module oneshot(osin,clk1,osout);
input osin;
input clk1;
output osout;
reg osout;
reg q;
always @(posedge osin or posedge osout)
begin
if(osout)
q <= 0;
else
q <= 1;
end
always @(posedge clk1)
begin
osout <= q;
end
endmodule