lfsrn11_rx.txt

these files are written in verilog but i am uploading in text format

`timescale 1ns/1ps
module lfsrn11_rx(q61_rx, clk1, load_rx);
output q61_rx;
input clk1 , load_rx;
reg q61_rx,q5_rx,q4_rx,q3_rx, q2_rx, q1_rx;
wire n2;
 assign n2=q1_rx ^ q61_rx;
always @(posedge clk1 or posedge load_rx )
if (load_rx) begin
     
      
q61_rx <= 1'b1;
q5_rx <= 1'b1;  
q4_rx <= 1'b1; 
q3_rx <= 1'b1;
q2_rx <= 1'b1;
q1_rx <= 1'b1;
 
  
end
else begin
  
q61_rx<=q5_rx;
q5_rx<=q4_rx;
q4_rx<=q3_rx;
q3_rx <= q2_rx;
q2_rx <= q1_rx;
q1_rx <= n2;
end
endmodule
 /*
module test_lfsrn11_rx;
    reg clk1,load_rx;
    wire q61_rx;
    lfsrn11_rx insta1(q61_rx, clk1, load_rx);
    initial
    begin
        clk1=1'b0;
        load_rx=1'b0;
        #40 load_rx=1'b1;
        
        #35load_rx=1'b0;
         
    end
    always
    #20clk1=~clk1;
endmodule  */