lfsrn12_rx.txt

these files are written in verilog but i am uploading in text format

`timescale 1ns/1ps
module lfsrn12_rx(q62_rx, clk1,load_rx);
output q62_rx;
input clk1 , load_rx;
reg q62_rx,q5,q4,q3, q2, q1;
wire n3;
 
assign n3 = q1 ^ q62_rx;
always @(posedge clk1 or posedge load_rx )
 
if ( load_rx) begin
 q62_rx <= 1'b1;
 q5 <= 1'b1;  
 q4 <= 1'b0; 
 q3 <= 1'b1;
 q2 <= 1'b0;
 q1 <= 1'b1;
  
end
else begin
 q62_rx<=q5;
 q5<=q4;
 q4<=q3;
 q3 <= q2;
 q2 <= q1;
 q1 <= n3;
end
endmodule