lfsrn11.txt

these files are written in verilog but i am uploading in text format

`timescale 1ns/1ps
module lfsrn11(q61, clk1, load);
output q61;
input clk1 , load;
reg q61,q5,q4,q3, q2, q1;
wire n1;
assign n1 = q1 ^ q61;
always @(posedge clk1 or posedge load  )
if (  load) begin
q61 <= 1'b1;
q5 <= 1'b1;  
q4 <= 1'b1; 
q3 <= 1'b1;
q2 <= 1'b1;
q1 <= 1'b1;
end
else begin
q61<=q5;
q5<=q4;
q4<=q3;
q3 <= q2;
q2 <= q1;
q1 <= n1;
end
endmodule