lfsrn12.txt

these files are written in verilog but i am uploading in text format

`timescale 1ns/1ps
module lfsrn12 (q62, clk1,load);
output q62;
input clk1 , load;
reg q62,q5,q4,q3, q2, q1;
wire n1;
assign n1 = q1 ^ q62;
always @(posedge clk1 or posedge load )
if (  load) begin
 q62 <= 1'b1;
 q5 <= 1'b1;  
 q4 <= 1'b0; 
 q3 <= 1'b1;
 q2 <= 1'b0;
 q1 <= 1'b1;
end
else begin
 q62<=q5;
 q5<=q4;
 q4<=q3;
 q3 <= q2;
 q2 <= q1;
 q1 <= n1;
end
endmodule