clock.txt

来自「these are verilog files but i am uploadi」· 文本 代码 · 共 21 行

`timescale 1ns/1ps
module clock(clk,clk1);
input clk;
output clk1;
reg clk1;
reg [10:0] clkDivCnt1=11'b0000_0000_000;
always @(posedge clk) 
begin
 
clkDivCnt1 <= clkDivCnt1 + 1;
if (clkDivCnt1==11'b1100_1011_011) 
begin
clk1<=1'b1;
clkDivCnt1<=11'b0000_0000_000;
end
else 
clk1<=1'b0;

end
endmodule