baud1.txt

来自「these are verilog files but i am uploadi」· 文本 代码 · 共 18 行

`timescale 1ns/1ps
module baud1(clk,baud);
input clk;
output baud;
reg baud;
reg [10:0] clkDivCnt=11'b0000_0000_000;
always @(posedge clk) 
begin
clkDivCnt <= clkDivCnt + 1;
if (clkDivCnt==11'b10100010110) 
begin
baud=1'b1;
clkDivCnt<=11'b0000_0000_000;
end
else 
baud=1'b0;
end
endmodule