baud16.txt

来自「these are verilog files but i am uploadi」· 文本 代码 · 共 21 行

`timescale 1ns/1ps
module baud16(clk,baud16);
input clk;
output baud16;
reg baud16;
reg [6:0] clkDivCnt5=7'b0000_000  ;
always @(posedge clk) 
begin
 
clkDivCnt5 <= clkDivCnt5 + 1;
if (clkDivCnt5==7'b1010_001) 
begin
baud16<=1'b1;
clkDivCnt5<=7'b0000_000 ;
end
else 
baud16<=1'b0;

end
endmodule