clk_8.txt

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`timescale 1ns/1ps
module clk_8(clk1,clk_8);
input clk1;
output clk_8;
reg clk_8;
reg [3:0] clkDivCnt8=4'b0000;
always @(posedge clk1) 
begin
 
clkDivCnt8 <= clkDivCnt8 + 1;
if (clkDivCnt8==4'b0111) 
begin
clk_8<=1'b1;
clkDivCnt8<=4'b0000;
end
else 
clk_8<=1'b0;

end
endmodule