📄 jtag_loader_rom_form.v
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// synthesis attribute INIT_11 of ram_1024_x_18 is "{INIT_11}"
// synthesis attribute INIT_12 of ram_1024_x_18 is "{INIT_12}"
// synthesis attribute INIT_13 of ram_1024_x_18 is "{INIT_13}"
// synthesis attribute INIT_14 of ram_1024_x_18 is "{INIT_14}"
// synthesis attribute INIT_15 of ram_1024_x_18 is "{INIT_15}"
// synthesis attribute INIT_16 of ram_1024_x_18 is "{INIT_16}"
// synthesis attribute INIT_17 of ram_1024_x_18 is "{INIT_17}"
// synthesis attribute INIT_18 of ram_1024_x_18 is "{INIT_18}"
// synthesis attribute INIT_19 of ram_1024_x_18 is "{INIT_19}"
// synthesis attribute INIT_1A of ram_1024_x_18 is "{INIT_1A}"
// synthesis attribute INIT_1B of ram_1024_x_18 is "{INIT_1B}"
// synthesis attribute INIT_1C of ram_1024_x_18 is "{INIT_1C}"
// synthesis attribute INIT_1D of ram_1024_x_18 is "{INIT_1D}"
// synthesis attribute INIT_1E of ram_1024_x_18 is "{INIT_1E}"
// synthesis attribute INIT_1F of ram_1024_x_18 is "{INIT_1F}"
// synthesis attribute INIT_20 of ram_1024_x_18 is "{INIT_20}"
// synthesis attribute INIT_21 of ram_1024_x_18 is "{INIT_21}"
// synthesis attribute INIT_22 of ram_1024_x_18 is "{INIT_22}"
// synthesis attribute INIT_23 of ram_1024_x_18 is "{INIT_23}"
// synthesis attribute INIT_24 of ram_1024_x_18 is "{INIT_24}"
// synthesis attribute INIT_25 of ram_1024_x_18 is "{INIT_25}"
// synthesis attribute INIT_26 of ram_1024_x_18 is "{INIT_26}"
// synthesis attribute INIT_27 of ram_1024_x_18 is "{INIT_27}"
// synthesis attribute INIT_28 of ram_1024_x_18 is "{INIT_28}"
// synthesis attribute INIT_29 of ram_1024_x_18 is "{INIT_29}"
// synthesis attribute INIT_2A of ram_1024_x_18 is "{INIT_2A}"
// synthesis attribute INIT_2B of ram_1024_x_18 is "{INIT_2B}"
// synthesis attribute INIT_2C of ram_1024_x_18 is "{INIT_2C}"
// synthesis attribute INIT_2D of ram_1024_x_18 is "{INIT_2D}"
// synthesis attribute INIT_2E of ram_1024_x_18 is "{INIT_2E}"
// synthesis attribute INIT_2F of ram_1024_x_18 is "{INIT_2F}"
// synthesis attribute INIT_30 of ram_1024_x_18 is "{INIT_30}"
// synthesis attribute INIT_31 of ram_1024_x_18 is "{INIT_31}"
// synthesis attribute INIT_32 of ram_1024_x_18 is "{INIT_32}"
// synthesis attribute INIT_33 of ram_1024_x_18 is "{INIT_33}"
// synthesis attribute INIT_34 of ram_1024_x_18 is "{INIT_34}"
// synthesis attribute INIT_35 of ram_1024_x_18 is "{INIT_35}"
// synthesis attribute INIT_36 of ram_1024_x_18 is "{INIT_36}"
// synthesis attribute INIT_37 of ram_1024_x_18 is "{INIT_37}"
// synthesis attribute INIT_38 of ram_1024_x_18 is "{INIT_38}"
// synthesis attribute INIT_39 of ram_1024_x_18 is "{INIT_39}"
// synthesis attribute INIT_3A of ram_1024_x_18 is "{INIT_3A}"
// synthesis attribute INIT_3B of ram_1024_x_18 is "{INIT_3B}"
// synthesis attribute INIT_3C of ram_1024_x_18 is "{INIT_3C}"
// synthesis attribute INIT_3D of ram_1024_x_18 is "{INIT_3D}"
// synthesis attribute INIT_3E of ram_1024_x_18 is "{INIT_3E}"
// synthesis attribute INIT_3F of ram_1024_x_18 is "{INIT_3F}"
// synthesis attribute INITP_00 of ram_1024_x_18 is "{INITP_00}"
// synthesis attribute INITP_01 of ram_1024_x_18 is "{INITP_01}"
// synthesis attribute INITP_02 of ram_1024_x_18 is "{INITP_02}"
// synthesis attribute INITP_03 of ram_1024_x_18 is "{INITP_03}"
// synthesis attribute INITP_04 of ram_1024_x_18 is "{INITP_04}"
// synthesis attribute INITP_05 of ram_1024_x_18 is "{INITP_05}"
// synthesis attribute INITP_06 of ram_1024_x_18 is "{INITP_06}"
// synthesis attribute INITP_07 of ram_1024_x_18 is "{INITP_07}"
// synthesis attribute INIT of srlC1 is "0000"
// synthesis attribute INIT of srlC2 is "0000"
// synthesis attribute INIT of srlC3 is "0000"
// synthesis attribute INIT of srlC4 is "0000"
// synthesis attribute INIT of srlC5 is "0000"
// synthesis attribute INIT of srlC6 is "0000"
// synthesis attribute INIT of srlC7 is "0000"
// synthesis attribute INIT of srlC8 is "0000"
// BSCAN_VIRTEX2 v2_bscan(
// .TDO1(tdo1),
// .TDO2(tdo2),
// .UPDATE(update),
// .SHIFT(shift),
// .RESET(reset),
// .TDI(tdi),
// .SEL1(sel1),
// .DRCK1(drck1),
// .SEL2(sel2),
// .DRCK2(drck2),
// .CAPTURE(capture));
BSCAN_SPARTAN3 v2_bscan(
.TDO1(tdo1),
.TDO2(tdo2),
.UPDATE(update),
.SHIFT(shift),
.RESET(reset),
.TDI(tdi),
.SEL1(sel1),
.DRCK1(drck1),
.SEL2(sel2),
.DRCK2(drck2),
.CAPTURE(capture));
//buffer signal used as a clock
BUFG upload_clock(
.I(drck1),
.O(drck1_buf));
// Assign the reset to be active whenever the uploading subsystem is active
assign proc_reset = sel1;
// synthesis translate_off
defparam srlC1.INIT = 16'h0000;
// synthesis translate_on
SRLC16E srlC1 (
.D(tdi),
.CE(1'b1),
.CLK(drck1_buf),
.A0(1'b1),
.A1(1'b0),
.A2(1'b1),
.A3(1'b1),
.Q(jaddr[10]),
.Q15(jaddr[8]))/* synthesis xc_props = "INIT=0000"*/;
FD flop1(
.D(jaddr[10]),
.Q(jaddr[9]),
.C(drck1_buf));
// synthesis translate_off
defparam srlC2.INIT = 16'h0000;
// synthesis translate_on
SRLC16E srlC2 (
.D(jaddr[8]),
.CE(1'b1),
.CLK(drck1_buf),
.A0(1'b1),
.A1(1'b0),
.A2(1'b1),
.A3(1'b1),
.Q(jaddr[7]),
.Q15(tap5))/* synthesis xc_props = "INIT=0000"*/;
FD flop2 (
.D(jaddr[7]),
.Q(jaddr[6]),
.C(drck1_buf));
// synthesis translate_off
defparam srlC3.INIT = 16'h0000;
// synthesis translate_on
SRLC16E srlC3(
.D(tap5),
.CE(1'b1),
.CLK(drck1_buf),
.A0(1'b1),
.A1(1'b0),
.A2(1'b1),
.A3(1'b1),
.Q(jaddr[5]),
.Q15(jaddr[3]))/* synthesis xc_props = "INIT=0000"*/;
FD flop3 (
.D(jaddr[5]),
.Q(jaddr[4]),
.C(drck1_buf));
// synthesis translate_off
defparam srlC4.INIT = 16'h0000;
// synthesis translate_on
SRLC16E srlC4 (
.D(jaddr[3]),
.CE(1'b1),
.CLK(drck1_buf),
.A0(1'b1),
.A1(1'b0),
.A2(1'b1),
.A3(1'b1),
.Q(jaddr[2]),
.Q15(tap11))/* synthesis xc_props = "INIT=0000"*/;
FD flop4 (
.D(jaddr[2]),
.Q(jaddr[1]),
.C(drck1_buf));
// synthesis translate_off
defparam srlC5.INIT = 16'h0000;
// synthesis translate_on
SRLC16E srlC5 (
.D(tap11),
.CE(1'b1),
.CLK(drck1_buf),
.A0(1'b1),
.A1(1'b0),
.A2(1'b1),
.A3(1'b1),
.Q(jaddr[0]),
.Q15(jdata[7]))/* synthesis xc_props = "INIT=0000"*/;
FD flop5 (
.D(jaddr[0]),
.Q(jparity[0]),
.C(drck1_buf));
// synthesis translate_off
defparam srlC6.INIT = 16'h0000;
// synthesis translate_on
SRLC16E srlC6(
.D(jdata[7]),
.CE(1'b1),
.CLK(drck1_buf),
.A0(1'b1),
.A1(1'b0),
.A2(1'b1),
.A3(1'b1),
.Q(jdata[6]),
.Q15(tap17))/* synthesis xc_props = "INIT=0000"*/;
FD flop6 (
.D(jdata[6]),
.Q(jdata[5]),
.C(drck1_buf));
// synthesis translate_off
defparam srlC7.INIT = 16'h0000;
// synthesis translate_on
SRLC16E srlC7 (
.D(tap17),
.CE(1'b1),
.CLK(drck1_buf),
.A0(1'b1),
.A1(1'b0),
.A2(1'b1),
.A3(1'b1),
.Q(jdata[4]),
.Q15(jdata[2]))/* synthesis xc_props = "INIT=0000"*/;
FD flop7 (
.D(jdata[4]),
.Q(jdata[3]),
.C(drck1_buf));
// synthesis translate_off
defparam srlC8.INIT = 16'h0000;
// synthesis translate_on
SRLC16E srlC8 (
.D(jdata[2]),
.CE(1'b1),
.CLK(drck1_buf),
.A0(1'b1),
.A1(1'b0),
.A2(1'b1),
.A3(1'b1),
.Q(jdata[1]),
.Q15(tdo1))/* synthesis xc_props = "INIT=0000"*/;
FD flop8 (
.D(jdata[1]),
.Q(jdata[0]),
.C(drck1_buf));
endmodule
//
////////////////////////////////////////////////////////////////////////////////////
//
// END OF FILE {name}.v
//
////////////////////////////////////////////////////////////////////////////////////
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