fenpin1.vhdl

此为EDA设计的分频器模块。可以实现三种不同的频率信号

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fenpin1 is
port(clk:in std_logic;
	clkout5:out std_logic;
	clkout10:out std_logic;
	clkout20:out std_logic);
end fenpin1;

architecture Behavioral of fenpin1 is
    signal clk1:std_logic:='0';
    signal clk2:std_logic:='0';
    signal clk3:std_logic:='0';
    signal q1:integer range 0 to 5:=0;
    signal q2:integer range 0 to 10:=0;
    signal q3:integer range 0 to 20:=0;

begin
t1:process(clk)
   begin
      if clk'event and clk='1'then
	    if q1=4 then
	        q1<=0;clk1<=not clk1;
	    else
	        q1<=q1+1;
	    end if;
	 end if;
   end process;
  clkout5<=clk1;

t2:process(clk)
   begin
      if clk'event and clk='1'then
	    if q2=9 then
	        q2<=0;clk2<=not clk2;
	    else
	        q2<=q2+1;
	    end if;
	 end if;
   end process;
   clkout10<=clk2;

t3:process(clk)
   begin
      if clk'event and clk='1'then
	    if q3=19 then
	        q3<=0;clk3<=not clk3;
	    else
	        q3<=q3+1;
	    end if;
	 end if;
   end process;
  clkout20<=clk3;
  
end Behavioral;