wave.ant

此为EDA设计的分频器模块。可以实现三种不同的频率信号

-- F:\DIANZIJISHUSHIYAN-DODO\FENPIN
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Tue Dec 30 20:07:23 2008

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY wave IS
END wave;

ARCHITECTURE testbench_arch OF wave IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "f:\dianzijishushiyan-dodo\fenpin\wave.ano";
	COMPONENT fenpin1
		PORT (
			clk : In  std_logic;
			clkout5 : Out  std_logic;
			clkout10 : Out  std_logic;
			clkout20 : Out  std_logic
		);
	END COMPONENT;

	SIGNAL clk : std_logic;
	SIGNAL clkout5 : std_logic;
	SIGNAL clkout10 : std_logic;
	SIGNAL clkout20 : std_logic;

BEGIN
	UUT : fenpin1
	PORT MAP (
		clk => clk,
		clkout5 => clkout5,
		clkout10 => clkout10,
		clkout20 => clkout20
	);

	PROCESS -- clock process for clk,
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_clkout5(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",clkout5,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, clkout5);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_clkout10(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",clkout10,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, clkout10);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_clkout20(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",clkout20,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, clkout20);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CLOCK_LOOP : LOOP
		clk <= transport '0';
		WAIT FOR 10 ns;
		TX_TIME := TX_TIME + 10;
		clk <= transport '1';
		WAIT FOR 10 ns;
		TX_TIME := TX_TIME + 10;
		ANNOTATE_clkout5(TX_TIME);
		ANNOTATE_clkout10(TX_TIME);
		ANNOTATE_clkout20(TX_TIME);
		WAIT FOR 40 ns;
		TX_TIME := TX_TIME + 40;
		clk <= transport '0';
		WAIT FOR 40 ns;
		TX_TIME := TX_TIME + 40;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clk
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION fenpin1_cfg OF wave IS
	FOR testbench_arch
	END FOR;
END fenpin1_cfg;