coregen.log

此为EDA设计的分频器模块。可以实现三种不同的频率信号

# Xilinx CORE Generator 6.2i
# User = LJ
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in F:\dianzijishushiyan-dodo\fenpin\coregen.log
NEWPROJECT .
SETPROJECT .
# busformat=BusFormatAngleBracketNotRipped
# designflow=VHDL
# expandedprojectpath=F:\dianzijishushiyan-dodo\fenpin
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=VHDL
# xilinxfamily=Virtex2
# outputoption=DesignFlow
# overwritefiles=Default
# simvendor=ModelSim
# expandedprojectpath=F:\dianzijishushiyan-dodo\fenpin
Set current Project to F:\dianzijishushiyan-dodo\fenpin
SET BusFormat = BusFormatAngleBracketNotRipped
SETXIPCPORTHOST 3130
XIPCPJSENDCORES spartan2