__projnav.log
来自「此为EDA设计的分频器模块。可以实现三种不同的频率信号」· LOG 代码 · 共 140 行
LOG
140 行
Project Navigator Auto-Make Log File-------------------------------------
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Project Navigator Auto-Make Log File-------------------------------------
Compiling vhdl file F:/fenpin/fenpin1.vhdl in Library work.Entity <fenpin1> (Architecture <Behavioral>) compiled.tdtfi(vhdl) completed successfully.
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Project Navigator Auto-Make Log File-------------------------------------
Compiling vhdl file F:/fenpin/fenpin1.vhdl in Library work.Entity <fenpin1> (Architecture <behavioral>) compiled.tdtfi(vhdl) completed successfully.
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Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
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Project Navigator Auto-Make Log File-------------------------------------
Compiling vhdl file F:/fenpin/fenpin1.vhdl in Library work.Entity <fenpin1> (Architecture <behavioral>) compiled.tdtfi(vhdl) completed successfully.
Project Navigator Auto-Make Log File-------------------------------------
Compiling vhdl file F:/fenpin/fenpin1.vhdl in Library work.Entity <fenpin1> (Architecture <behavioral>) compiled.tdtfi(vhdl) completed successfully.
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Started process "Create Schematic Symbol".Compiling vhdl file F:/dianzijishushiyan-dodo/fenpin/fenpin1.vhdl in Librarywork.Entity <fenpin1> (Architecture <behavioral>) compiled.tdtfi(vhdl) completed successfully.
Release 6.2i - spl2sym G.28Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Completed process "Create Schematic Symbol".
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Project Navigator Auto-Make Log File-------------------------------------
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