fenpin.npl

来自「此为EDA设计的分频器模块。可以实现三种不同的频率信号」· NPL 代码 · 共 26 行

JDF G
// Created by Project Navigator ver 1.0
PROJECT fenpin
DESIGN fenpin
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s100
DEVICETIME 0
DEVPKG pq208
DEVPKGTIME 0
DEVSPEED -5
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE fenpin1.vhdl
STIMULUS test.vhd
STIMULUS wave.tbw
[STRATEGY-LIST]
Normal=True