test.vhd

此为EDA设计的分频器模块。可以实现三种不同的频率信号

-- VHDL Test Bench Created from source file fenpin1.vhd -- 17:02:31 09/20/2008
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY fenpin1_test_vhd_tb IS
END fenpin1_test_vhd_tb;

ARCHITECTURE behavior OF fenpin1_test_vhd_tb IS 

	COMPONENT fenpin1
	PORT(
		clk : IN std_logic;          
		clkout16 : OUT std_logic;
		clkout32 : OUT std_logic;
		clkout64 : OUT std_logic
		);
	END COMPONENT;

	SIGNAL clk :  std_logic;
	SIGNAL clkout16 :  std_logic;
	SIGNAL clkout32 :  std_logic;
	SIGNAL clkout64 :  std_logic;

BEGIN

	uut: fenpin1 PORT MAP(
		clk => clk,
		clkout16 => clkout16,
		clkout32 => clkout32,
		clkout64 => clkout64
	);


-- *** Test Bench - User Defined Section ***
   tb : PROCESS
   BEGIN
      clk<='0';wait for 10 ns;
	 clk<='1';wait for 10 ns;  
   END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;