clk_div.vhd

VHDL描述的时钟分频电路

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:48:07 03/30/2009 
-- Design Name: 
-- Module Name:    clk_div - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity clk_div is
    Port ( CLK_50M : in  STD_LOGIC;
           RST_IN : in  STD_LOGIC;
           CLK_OUT0 : out  STD_LOGIC);
end clk_div;

architecture Behavioral of clk_div is
	COMPONENT CLK_221184_GEN			
	PORT(
		CLKIN_IN : IN std_logic;
		RST_IN : IN std_logic;          
		CLKFX_OUT : OUT std_logic			--Clk gen 22.1184M
--		CLKFX180_OUT : OUT std_logic;
--		CLKIN_IBUFG_OUT : OUT std_logic;
--		CLK0_OUT : OUT std_logic;
--		LOCKED_OUT : OUT std_logic
		);
	END COMPONENT;

	SIGNAL clk_221184 : STD_LOGIC;
	SIGNAL full : STD_LOGIC;

begin
p_reg: process(clk_221184) 
			VARIABLE cnt25: STD_LOGIC_VECTOR(24 downto 0);   --clk_div coeffient is 1_0101_0001_1000_0000_0000_0000 :11059200x2
			begin
				if RST_IN = '1' then 
					cnt25 := "0000000000000000000000000";
					full <= '0';
				elsif clk_221184'event and clk_221184='1' then
					if cnt25 = "1010100011000000000000000" then
						cnt25 := "0000000000000000000000000";
						full <= '1';
					else
						cnt25 := cnt25 + '1';
						full <= '0';
					end if;
				end if;
			end process p_reg;
			
p_out: process(full)
			VARIABLE CNT2 : STD_LOGIC;
		 begin
			if RST_IN = '1' then
				CNT2 := '0';
			elsif full'event and full='1' then
				CNT2 := not CNT2;
			else
				CNT2 := CNT2;
			end if;
			
			CLK_OUT0 <= CNT2;
		end process p_out;
		
			
	
	
   Inst_CLK_221184_GEN: CLK_221184_GEN PORT MAP(
		CLKIN_IN =>CLK_50M ,
		RST_IN =>RST_IN ,
		CLKFX_OUT =>clk_221184 
--		CLKFX180_OUT => ,
--		CLKIN_IBUFG_OUT => ,
--		CLK0_OUT => ,
--		LOCKED_OUT => 
	);
			

end Behavioral;