hz.v

万能频率器

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    19:12:10 03/10/2009 
// Design Name: 
// Module Name:    hz 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module hz(clk,f1hz,f500hz);
    input clk;         //输入频率为50mhz

    output f1hz,f500hz;

    reg f1hz,f500hz;
    integer cnt1,cnt2;//ji shu 
	 initial
	  begin
	    cnt1=0;
		 cnt2=0;
		 end

    always@(posedge clk)
    begin
		  if (cnt1 < 50000 )
		     begin
			     cnt1 = cnt1+1;
			  end
		  else
		     begin
			     f500hz = ~f500hz;
				  cnt1 = 0;
			 end          
   end

   always@(posedge f500hz)
   begin
	     if(cnt2 < 250)
		      cnt2 = cnt2+1;
		  else
		     begin
			    f1hz = ~f1hz;
				 cnt2 = 0;
			 end
   end


endmodule