moore1.v

moore 状态机的一个简单的事例

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    10:54:49 03/16/2009 
// Design Name: 
// Module Name:    moore1 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module moore1(CLK,Din,RESET,Qout);
    input CLK;
    input Din;
    input RESET;
    output Qout;
    reg Qout;
	 //declear the vale for all states
	 parameter [1:0]
	 S0=2'b00,
	 S1=2'b01,
	 S2=2'b10,
	 S3=2'b11;
	 // declear current state and next state variables
	 reg [1:0] CS;
	 reg [1:0] NS;
	 
	 always @(posedge CLK or posedge RESET)
	    begin 
		   if(RESET==1'b1)
			  CS=S0;    //initial state
			else
			  CS=NS;
		 end
		 
	 always @(CS or Din)
	    begin 
		  case (CS)
		    S0:begin
			       Qout=1'b0;
			         if(Din==1'b0)
			            NS=S0;
				      else
				         NS=S2;
				 end
			 
			 S1:begin
			       Qout=1'b1;
			         if(Din==1'b0)
			            NS=S0;
				      else
				         NS=S2;
				end
           
			 S2:begin
			       Qout=1'b1;
			         if(Din==1'b0)
			            NS=S2;
				      else
				         NS=S3;
				end				
	 
           S3:begin
			       Qout=1'b0;
			         if(Din==1'b0)
			            NS=S3;
				      else
				         NS=S1;
		        end
		endcase
     end
endmodule