mealy1.v

来自「mealy 状态机的独热编码源程序」· Verilog 代码 · 共 91 行

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    19:26:40 03/16/2009 
// Design Name: 
// Module Name:    mealy1 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module mealy1(CLK,Din,RESET,Qout);
    input CLK;    
    input RESET;
	 input Din;
    output Qout;
    reg Qout;
	//decleare the value for all states 
	 parameter [1:0]
	 S0=2'b00,
    S1=2'b01,
	 S2=2'b11;
	//decleare current state and next state variables 
	 reg[1:0] CS;
	 reg[1:0] NS;
	 
	 always @(posedge CLK or posedge RESET)
	    begin 
		    if(RESET==1'b1)
		       CS=S0;   //initial state
			 else
			    CS=NS;
		 end
		 
		 always @(CS or Din)
		   begin
			  case(CS)
				 S0:begin
				      if(Din==1'b0)
						    begin
						       Qout=0;
						       NS=S0;
					       end
						 else
						    begin
							    Qout=0;
								 NS=S1;
							 end
						 end 
				      
				 S1:begin
				      if(Din==1'b0)
						    begin
						       Qout=1'b0;
						       NS=S2;
					       end
						 else
						    begin
							    Qout=1'b0;
								 NS=S1;
							 end
						 end 
				  
				  S2:begin
				      if(Din==1'b0)
						    begin
						       Qout=1'b0;
						       NS=S0;
					       end
						 else
						    begin
							    Qout=1'b1;
								 NS=S1;
							 end
						 end 
				   endcase
			end
					
				        

endmodule