adder8.v

来自「Vrilog HDL 八位加法器源程序」· Verilog 代码 · 共 46 行

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    20:30:19 03/12/2009 
// Design Name: 
// Module Name:    adder8 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module adder8(cin,a,b,sum,cout);
    parameter length=8;
	 input cin;
    input [length-1:0] a;
    input [length-1:0] b;
    output [length-1:0] sum;
    output cout;
	 reg carry;       //internal carry
	 integer i;      //loop parameter
	 
	 reg[length-1:0] sum;
	 reg cout;
	 
	 always @(a or b or cin or carry)
	 begin
	   carry=cin;
		for(i=0;i<length;i=i+1)
		  begin
		    sum[i]=a[i] ^b[i] ^carry;
			 carry=a[i] & b[i] | a[i] & carry | b[i] & carry;
        end
     cout=carry;
     end

endmodule