counter.v

一个用数码管自动计数的verilog程序

module counter(CLOCK_50,HEX0,HEX1,KEY0);

	input	CLOCK_50;
	input   KEY0;
	output	[6:0]HEX0,HEX1;
	reg		[3:0]counter_0,counter_1;
	reg		[6:0]HEX0,HEX1;
	reg		[27:0]	Cont;
	reg     counter_2;
initial 
	begin
		counter_0=0;
		counter_1=0;
		HEX0=7'b1000000;
		HEX1=7'b1000000;
	
		Cont=0;
		counter_2=0;
	end
/*	always@(negedge KEY1)
	begin
	counter_2=~counter_2;
    end
*/
always@(posedge CLOCK_50)	
	begin
	if(!KEY0)
	begin		
		
		HEX0=7'b1000000;
		HEX1=7'b1000000;		
		
	end	
/*	else
	if(counter_2)
	begin
	Cont=Cont;
	counter_0=counter_0;
	counter_1=counter_1;
	end
*/
	else
		if(Cont==50000000)
			begin	
				
			counter_0=counter_0+1;
			Cont	<=	0;
			
			case(counter_0)
			
			4'b0000:	HEX0=7'b1000000;
			4'b0001:	HEX0=7'b1111001;
			4'b0010:	HEX0=7'b0100100;
			4'b0011:	HEX0=7'b0110000;
			4'b0100:	HEX0=7'b0011001;
			4'b0101:	HEX0=7'b0010010;
			4'b0110:	HEX0=7'b0000010;
			4'b0111:	HEX0=7'b1111000;
			4'b1000:	HEX0=7'b0000000;
			4'b1001:	HEX0=7'b0010000;
			4'b1010:	begin
						HEX0=7'b1000000;
						counter_0=0;
						counter_1=counter_1+1;
						end
			endcase
			
			case(counter_1)
			
			4'b0000:	HEX1=7'b1000000;
			4'b0001:	HEX1=7'b1111001;
			4'b0010:	HEX1=7'b0100100;
			4'b0011:	HEX1=7'b0110000;
			4'b0100:	HEX1=7'b0011001;
			4'b0101:	HEX1=7'b0010010;
			4'b0110:	HEX1=7'b0000010;
			4'b0111:	HEX1=7'b1111000;
			4'b1000:	HEX1=7'b0000000;
			4'b1001:	HEX1=7'b0010000;
			4'b1010:	begin
						HEX1=7'b1000000;
						counter_1=0;
						end
			endcase
			end
		else
			Cont	<=	Cont+1;
	end

/*always@(clock )
	begin
		if(!reset)
			begin
				counter_0=0;
				counter_1=0; 
				HEX0=7'b1000000;
				HEX1=7'b1000000;
			end
		else

			begin		
			 counter_0=counter_0+1;
			case(counter_0)
			
			4'b0000:	HEX0=7'b1000000;
			4'b0001:	HEX0=7'b1111001;
			4'b0010:	HEX0=7'b0100100;
			4'b0011:	HEX0=7'b0110000;
			4'b0100:	HEX0=7'b0011001;
			4'b0101:	HEX0=7'b0010010;
			4'b0110:	HEX0=7'b0000010;
			4'b0111:	HEX0=7'b1111000;
			4'b1000:	HEX0=7'b0000000;
			4'b1001:	HEX0=7'b0010000;
			4'b1010:	begin
						HEX0=7'b1000000;
						counter_0=0;
						counter_1=counter_1+1;
						end
			endcase
			
			case(counter_1)
			
			4'b0000:	HEX1=7'b1000000;
			4'b0001:	HEX1=7'b1111001;
			4'b0010:	HEX1=7'b0100100;
			4'b0011:	HEX1=7'b0110000;
			4'b0100:	HEX1=7'b0011001;
			4'b0101:	HEX1=7'b0010010;
			4'b0110:	HEX1=7'b0000010;
			4'b0111:	HEX1=7'b1111000;
			4'b1000:	HEX1=7'b0000000;
			4'b1001:	HEX1=7'b0010000;
			4'b1010:	begin
						HEX1=7'b1000000;
						counter_1=0;
						end
			endcase
			end*/


endmodule