h_adder.vhd

来自「8位全加器的VHDL语言描述」· VHDL 代码 · 共 23 行

library ieee;
use ieee.std_logic_1164.all;
entity h_adder is
port(a,b:in std_logic;
     co,so:out std_logic);
end entity h_adder;
architecture fh1 of h_adder is 
signal abc:std_logic_vector(1 downto 0);
begin 
abc<=a&b;
process(abc)
begin 
case abc is
  when"00"=>so<='0';co<='0';
  when"01"=>so<='1';co<='0';
  when"10"=>so<='1';co<='0';
  when "11"=>so<='0';co<='1';
  when others=>null;
end case;
end process;
end architecture fh1;