mux8.vhd

8位全加器的VHDL语言描述

library ieee;
use ieee.std_logic_1164.all;
entity mux8 is
port(i0,i1,i2,i3,i4,i5,i6,i7,a,b,c:in std_logic;
     q:out std_logic);
end mux8;
architecture body_mux8 of mux8 is
begin
process(i0,i1,i2,i3,i4,i5,i6,i7,a,b,c)
variable muxval:integer range 7 downto 0;
begin  muxval:=0;
if(a='1')then muxval:=muxval+1;end if;
if(b='1')then muxval:=muxval+2;end if;
if(c='1')then muxval:=muxval+4;end if;
case muxval is
    when 0=>q<=i0;
    when 1=>q<=i1;
    when 2=>q<=i2;
    when 3=>q<=i3;
    when 4=>q<=i4;
    when 5=>q<=i5;
    when 6=>q<=i6;
    when 7=>q<=i7; 
    when others=>null;
end case;
end process;
end body_mux8;