adder8.vhd

8位全加器的VHDL语言描述

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY adder8 IS
	PORT(
		cin:IN STD_LOGIC;
		a:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		b:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		cout:OUT STD_LOGIC;
		s:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
		);
END adder8;
ARCHITECTURE behav OF adder8 IS
	COMPONENT f_adder
	PORT(ain,bin,cin:IN STD_LOGIC;
		cout,sum:OUT STD_LOGIC);
	END COMPONENT;

	SIGNAL cout_temp:STD_LOGIC_VECTOR(6 DOWNTO 0);
	BEGIN
	    adder0_map:f_adder PORT MAP(a(0),b(0),cin,cout_temp(0),s(0));
        adder1_map:f_adder PORT MAP(a(1),b(1),cout_temp(0),cout_temp(1),s(1));
        adder2_map:f_adder PORT MAP(a(2),b(2),cout_temp(1),cout_temp(2),s(2));
        adder3_map:f_adder PORT MAP(a(3),b(3),cout_temp(2),cout_temp(3),s(3));
        adder4_map:f_adder PORT MAP(a(4),b(4),cout_temp(3),cout_temp(4),s(4));
        adder5_map:f_adder PORT MAP(a(5),b(5),cout_temp(4),cout_temp(5),s(5));
        adder6_map:f_adder PORT MAP(a(6),b(6),cout_temp(5),cout_temp(6),s(6));
        adder7_map:f_adder PORT MAP(a(7),b(7),cout_temp(6),cout,s(7));
	
END ARCHITECTURE behav;