or2a.vhd

来自「8位全加器的VHDL语言描述」· VHDL 代码 · 共 12 行

library ieee;
use ieee.std_logic_1164.all;
entity or2a is
port(a,b:in std_logic;
     c:out std_logic);
end entity or2a;
architecture one of or2a is 
begin
c<=a or b;
end architecture one;